Reading and writing a local variable in the same Single Cycle Timed Loop

[jordani]

They are read/write access to a memory location - however that "memory" is handled in the FPGA…

Do we know then if the value is shifted from memory to the SCTL when the iteration begins and is then shifted back when the SCTL finishes? This is what I thought should happen and would maintain dataflow.

[GerdW]

Hi jordani,

Do we know then if the value is shifted from memory to the SCTL when the iteration begins and is then shifted back when the SCTL finishes?

Why should that happen? There is absolutely NO DATAFLOW dependency between your read and write operation!

That's why I suggest to use a shift register to get rid of the concurrent read and write to the very same local variable! It all boils down to just one write operation…

[jordani]

I think that it may happen because in several places NI implies that a local variable may be arbitrated and that it could be used to cross clock domains(handshaking). This implies that there is more going on than just direct access to logic on the FPGA. I also think that it is usual practice(when using HDLs) to register values into and out of a clocked event like the SCTL so that a combinatorial circuit is not created. For example: NI recommends the use of (and enables by default) syncronizing registers on the DIO pins which avoids this issue when writing the value of a DIO based upon value(s) read from other DIOs.

I agree that the use of shift registers results in more explicit code (so I've changed my approach). I'm also aware that issues such as crossing clock domains and synchronicity require careful management in FPGA code. I'm frustrated that the documentation is somewhat vague on the subject; the input of those having more experience is greatly appreciated.

Thanks again.