07-30-2013 07:11 AM
Dear Sir,
Since past 2 months I am facing a problem in data transfer in cRIO 9073.
I'm using two c series modules for data acquisition. NI 9205 for analog input and NI 9421 for digital input. Where Max sample rate of 9205 is 250kS/s.
All seems perfect from FPGA to RT data transfer using FIFO. I m able to read instant value in RT when I change given input. In FPGA I m successfully reading and transferring 32 samples per 200us. In RT I m reading 16000 samles from FIFO and push it into shared variable. (No time out occurs in FIFO) therefore all I can say I m acquiring perfectly till RT.
But when I tries to transfer dta from RT to HOST, at the time I m facing a problem. Host is updating 3-4 seconds late than RT. I have tried shared variable, TCP & Network steaming & faced same problem in all the cases.
I m not able to get that where the problem is? Because I can see instant change as per input in RT. dont know what happened between RT to Host data transferring.
Please do let me know what can be the possible reasons. Crossover Ethernet port or cable or chassis data transfer rate what can be the cause?????
Regards,
Pranav Parik
Application Engineer
Alliance Partner of National Instruments
07-30-2013 10:22 AM
What is the priority of the VI you're running? I'd be concerned that maybe you've starved out the ethernet transmit thread or something.
-Danny