RT to FPGA data transfer via DMA FIFO

[KieranW]

Hello,

I am trying to send data via DMA FIFO to the FPGA from an RT. The data is the values for a sine wave with given parameters, and is single floating point data created within a for loop.

The issue is the DMA FIFO invoke node on the RT (Write) requires an array of data. I know I can just auto-index out and then wire the data in, but at the read end on the FPGA it is expecting just a single value per call - is this going to cause an issue with values being lost?

For context, the data is then being wired into a look-up table on the FPGA for continuous use. If there is a better way of doing this, please let me know.

Any help would be greatly appreciated.

[nathand · Accepted solution]

It would help to see your code; this sounds like an inappropriate use of a DMA FIFO. Probably you should use a front panel control instead for transferring a single value; you can add a handshaking boolean if you need to confirm that the FPGA read the value before moving on to the next value.

Access to a DMA FIFO is always through an array on the host (RT) side, and through individual elements on the FPGA. That way the host side can process a bunch of elements as a group, efficiently, while the FPGA generates or reads them individually. There is no loss of data unless the DMA FIFO overflows (runs out of space).

[KieranW]

I've attached the VI from the RT side and an image of the relevant code on the FPGA side.

Would front panel communication be suitable for sending an unknown sized array?

[ikaiser]

At least for me, there is a lot of open questions. What's the throughput you need? Only updating the lookup table once in a while or all the time? Do you need to be sure the new lookup table is written when other parts of your fpga code do not read the table (like vsync in display technology)? What do you mean with "unknown size"? Does your FPGA code get triggered from RT when there is new data, and do you check that the fifo was empty before?

In general, your solution looks reasonable, however a frontpanel object could also be used: Transferring Data Using Front Panel Controls and Indicators (FPGA Module). Be aware that this has limitations, might not the best solution, and is generally not recommended when using arrays on frontpanel objects: Limiting the Number of Top-Level Front Panel Objects in FPGA VIs (FPGA Module)

[KieranW]

The Lookup table only needs updating when some modulation configuration settings are updated - triggering the "Gen Waveform" boolean. This is infrequent. As it stands, it won't be written to whilst the lookup-table is being updated because the updating will have occured before any reading is done and the controls to update config settings and trigger the re-write are disabled while the function that requires reading is in operation.

The number of points in the waveform is governed by a frequency that is selected, anywhere from 64 up to 2048 points. The lookup table is large enough to accomodate this and the function that reads the table also knows to only read the required number of samples. What I meant to say is that the array size is going to be variable based on the number of points I require in each waveform.

[crossrulz · Accepted solution]

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@KieranW wrote:

Would front panel communication be suitable for sending an unknown sized array?

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No.  On an FPGA, all arrays have to be fixed in size.  You are defining hardware when you program and FPGA.  Just stick with the DMA FIFO.  It will likely use less resources and you will not miss updates on the RT side (assuming you are not really slow and allow the FIFO to overrun).

[nathand · Accepted solution]

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@KieranW wrote:

I've attached the VI from the RT side and an image of the relevant code on the FPGA side.

Would front panel communication be suitable for sending an unknown sized array?

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What I was suggesting was that rather than putting the entire array as a front-panel item, you instead put a single element on the front panel, along with a boolean for confirming that the value has been set (NI refers to this as handshaking, or at least they used to, although it seems like most of the documents that referred to it that way have been moved or deleted). You might also put a memory address/array index on the front panel if you want to update only a few memory addresses at a time. On your FPGA, you have a loop that sits waiting for the boolean to be true. When it is true, you update the next (or the specified) memory address with the value from the front panel, then set the boolean false. The RT side sees that the boolean is false and writes the next value (and address) to the front panel control, then sets the boolean true again, etc.

While this is slower than a DMA transfer, it is efficient in resource use and good for situations where you don't need to stream data constantly, especially if you're running low on DMA channels. There's an example here: https://forums.ni.com/t5/Example-Program-Drafts/Handshaking-with-LabVIEW-FPGA/ta-p/3515124

[KieranW]

Ah I see, thanks for the suggestion and information.

I hadn't considered doing it that way.