When attaching a project, it might be best to zip the project folder, or attach your VIs, so that we can look at your code. As for the screenshot, it looks like you might be using too many resources on the FPGA but again it is hard to determine without looking at your code.
Since you are using a myRIO, you might get better responses by posting to the Academic Hardware Products forum as this handles many myRIO questions.
Also, there are many pre-built project templates and examples within LabVIEW that might be worth exploring as well as a project guide that includes many tuturials. You can find the latter here.