Question about sinchronization of samples taken by C Series Modules using cRIO

[el_tlatoani]

Hello for my thesis project I need to acquire signals from various sensors at different sampling rates using the cRIO. So far, my acquisition is running well. However, I am still unsure whether the samples taken are synchronized.

I am using:

NI-9223 and NI-9222 C Series Modules

On the FPGA VI I am using the user-controlled IO sampling functions to achieve the maximum sample rate from both cards (1MS/s/ch and 500kS/s/ch respectively).

Based on the code attached I would expect that the pulse generating loop waits the specified number of microseconds and then generates the pulse. Taking into account the the 1MS/s Loop takes its first sample 1 microsecond earlier than the 500kS/s Loop, I would like to know if the first sample of the 500kS/s Loop will be taken at the exact same time as the second sample of the 1MS/s Loop.

[l.hovs]

Hi el_tlatoani, 

After analyzing your code, I see that the 500KS/s loop waits constant is set 2 microseconds, because of that you have non synchronized sampling, to achieve desired synchronization you should put the 500KS/s loop to wait as long as the first one (in this case 1 microsecond).

Regards)

[ZYOng]

The easiest way would be putting I/Os of both modules into the same loop. You can put your faster loop inside your slower loop, and run the faster loop a fixed number of times for each iteration of the slower outside loop. Then the two loops will synchronize every iteration of the slower loop (which is the same as every n iterations of the faster loop).

Reference: https://forums.ni.com/t5/LabVIEW/FPGA-Synchronization-between-two-loops-with-different-loop-rates/m-...