Hi all. I have a weird problem with my FPGA system. I am a complete starter in this field, so please take it into account. So my problem is - I have developed a project with cRIO-9074. I have 6 C modules, all of them run on FPGA. I have developed a code both for FPGA side and Host PC side. The weird thing is, that when I run my Host VI code in simulation mode everything is fine. I can control DO, I get data from FPGA VI (of course, they are random, bu still). When I choose "FPGA Target" mode in "Select execution mode" menu, and enter my FPGA VI I can read data, and control eerything, so everything is smooth and fine. BUT, when I open my Host VI code, and I run it I have no data comming from cRIO. I also don't think it comunicates with cRIO, cause when I FPGA VI while Host is running, I can see that FPGA is not running. And I can not force it to start. Can you suggest me a possible solution? Thank you in advance.
I have added the screen shot of my Host and FPGA VI. I know they are a bit messy, but I just want my system to work cause the deadline is really close.
Solved! Go to Solution.
I see something odd on the FIFO read on the host side.
You check the number of elements in the FIFO and Q&R divide by 2. But then use the remainder to determine how many to read which will either be 1 or 0.
I believe you want to use the quotient so that you always read in multiples of two.
You are resetting your FPGA with every iteration of your host loop. Get rid of that Reset method.
Thanks a lot, now everything works fine.
At the same time I have some small problem with reading a frequency of the grid with NI 9242 module. I have seen an example provided by NI of how to use the NI 9242 module. And in that example the block "Build waveform" is used and a "dt" value there is (1/frame rate), which obvious and understandble. However, if I use the frame rate of 50 kS/s I got the wrong value of frequency of the grid (which is 50 Hz for sure). I receive 50 Hz with "dt" of 31244. Any clues for that?