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11-29-2017 02:06 AM

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The fpga can't use the Quotient & Remainder that's right? , how can i do the same operation without Quotient & Remainder.

And another question, the fpga doesn't support the tome stamp type of data???

11-29-2017 02:46 AM - edited 11-29-2017 02:48 AM

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Hi Cristina,

how can i do the same operation without Quotient & Remainder.

Depends on the numbers you want to have quotient&remainder with!

With powers of 2 you can use simple boolean operations (AND/OR) and shift operations.

With "random" numbers you can do, what you have learned back in primary school…

fpga doesn't support the tome stamp type

What do you need timestamps for on FPGA?

Hint: the FPGAS can count clock cycles very easily…

Best regards,

GerdW

CLAD expired, using LV2011SP1 + LV2017 (+LV2019 sometimes) on Win7+cRIO

Kudos are welcome

GerdW

CLAD expired, using LV2011SP1 + LV2017 (+LV2019 sometimes) on Win7+cRIO

Kudos are welcome

11-29-2017 02:54 AM

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I want to do that u have learned back in primary schhol as you say, but, with the divisoin block i obtain a decimal number, for example if i divide 5 betwwen 3 the result is 1,5 and i want that the result will be 1 for then calculate the remaind.

How can i count the cycle in fpga?

Sorry, i'm new in labview

11-29-2017 02:59 AM

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11-29-2017 03:08 AM - edited 11-29-2017 03:12 AM

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Hi Cristina,

if i divide 5 betwwen 3 the result is 1,5

How do you get 1.5 as result of 5/3???

You seem to use different math than me…

i want that the result will be 1 for then calculate the remaind.

Using the algorithm I linked to before will give you this answer!

while N ≥ D do N := N − D end return N

All you need to do is to count the number of subtract operations to get the quotient…

How can i count the cycle in fpga? Sorry, i'm new in labview

Then you should take the beginner courses and all those AppNotes related to LabVIEW RealTime and LabVIEW FPGA module!

Counting cycles is easy: use a loop (SCTL) and count it's iterations…

Best regards,

GerdW

CLAD expired, using LV2011SP1 + LV2017 (+LV2019 sometimes) on Win7+cRIO

Kudos are welcome

GerdW

CLAD expired, using LV2011SP1 + LV2017 (+LV2019 sometimes) on Win7+cRIO

Kudos are welcome

11-29-2017 03:13 AM

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Sorry, 1,66666 ....

11-29-2017 06:04 AM

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As we stated in your other thread, the Quotient & Remainder is supported on the FPGA. However, it uses multiple cycles to complete and it therefore cannot be put into a Single Cycle Timed Loop (SCTL).

Now as far as counting time, you can simply use a shift register to keep a counter. If on a SCTL, then you know what the loop rate is. You can do simple math from there.

There are only two ways to tell somebody thanks: Kudos and Marked Solutions

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