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Practical limit of 'Programmatic FPGA Interface Communication' or me being dumb?

Hello,

I'm using a cRIO-9074 and 9505 module to do closed loop position control of an actuator.  I based my original code on the NI example 'Position Control (closed loop) - NI 9505'.  Everything was working great.

 

Now I'm trying to move some of the code (current and position control loops) onto the RT processor and off of the gate array.  The reason for this is because I'm writing some special PID code and can't wait 30 minutes to recompile the FPGA VI every time I make a change.

 

Documentation says that 'Programmatic FPGA Interface Communication', a.k.a. 'FPGA Read/Write', is good for frequent scalar data transfers.  That's what I'm doing but I'm attempting to do it every 20kHz and feed the result to the PWM duty cycle loop on the gate array.  The loop shown in the attached code won't come anywhere close to a 50us period.  It's slow by several orders of magnitude even when it's the only thing running on the RT processor.  If I try running it at 50us (20kHz), the loop doesn't report that it finished late but the cRIO controller locks up and won't do anything until I cycle the power.  Can DMA do what I'm attempting to do?  Buffering won't help because I need (nearly) instantaneous data to feed the PID loop.

 

It seems like it should be really easy to transmit really up-to-date data back and forth between the FPGA and the RT processor...  Am I missing something?

 

Thanks,

Ethan

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Hi Ethan,

 

I would recommend that you use DMA since the data transfers are much faster and there is proper FIFO/queue implementation provided when doing so. I won't be able to say if it will work well since I don't have the hardware in front of me, but in my experience, if you program it right, it would work much better than FPGA Read/Write. Have a look at some example programs before you start programming to get an idea of what the best implementations might be.

 

Also, there is a Benchmark Project example available in the Example Finder that uses an assembly-level call to obtain precise timestamps from RT targets. The purpose of the example is to gather timing information on a user's VI by running it for several iterations. That could be useful to help you figure out where things might be going wrong.

Adnan Zafar
Certified LabVIEW Architect
Coleman Technologies
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Adnan Z,

 

Thank you for the response.  Follow-up question:

 

Does anyone know if multiple FPGA R/W controls can operate in parallel?  I have multiple loops reading and writing to the FPGA.  They should operate in parallel but perhaps the FPGA R/W controls are a bottleneck?  I'm assuming that under the hood, the RT processor is serially reading and writing to the FPGA and that would explain the relatively crappy throughput I'm getting.  I'm going to try writing all of my variables to a DMA array and reading them all at once every 20kHz.  Sound reasonable?

 

Thanks,

Ethan

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Hello,

 

It seems that this could cause a possible race conditions because the processor is trying to serialize these two accesses. Here and Here are two kb's that describe this process. Hope this helps.

 

Regards,

National Instruments
RIO Embedded Hardware PSE

CompactRIO Developers Guide
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Hi estern,

 

Also, just to be sure you said you were placing some custom PID on the rt side because you can't wait 30 min for compiles.  Have you tried simulating the FPGA side.  Obviously there are limitations (timing, coordinating back to the rt side, etc) when you simulate, but if it is just testing the algorithm with known inputs typically that is good enough.  Just checking 🙂

"If you want to succeed... Architect" - The Specialist
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Thank you for the responses.  I seem to be getting along okay using lower loop rates but I still don't understand why the throughput from the FPGA to the RT processor is so miserable.  Anyone have experience using DMA transfers at >1kHz?  I'm not talking about a lot of data here, just a few I16's being read and written once per loop iteration.  I can't find any examples that use DMA for immediate data transfer.

 

I have tried simulating the FPGA code on my PC but it crashes my system without fail.  Perhaps a reinstall of LabVIEW would cure that problem but I haven't had the patience.

 

Ethan

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Hi Ethan,

 

You will definately be able to write data MUCH faster than 1Khz on the fpga side. The problem comes in tuning your system so that it reads or writes enough data on the RT side. You had to read/write big enough chunks of data on the RT side to keep up with the speed of your fpga. "By monitoring the Elements Remaining output, one can determine if the host loop should be run at a faster rate or if more samples should be read per loop iteration".  Here is a DevZone that describes high speed fifo transmission.

 

 

National Instruments
RIO Embedded Hardware PSE

CompactRIO Developers Guide
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