Possible to generate stimulus from HDL testbench on Host VI?

[MrMYH]

I have an HDL design with an HDL testbench. I want to port them to an NI board with LabVIEW. Thus, I create an FPGA VI and import the HDL design by component-level IP (CLIP). However, I have trouble to create a host VI as testbench. I searched LabVIEW documents. It seems that there is no way to run the HDL testbench on host and generate stimulus to FPGA VI through the host VI. It means I can't reuse the HDL testbench to drive the FPGA VI and so I have to write an equivalent LabVIEW testbench. Is this true?

Actually, I have an FPGA board from a vendor, which supports communication with MathWorks Simulink. Furthermore, Simulink supports cosimulation with ModelSim. Thus, I can reuse my HDL testbench to generate stimulus from ModelSim to Simulink and then pass them from Simulink to the FPGA board. No need to rewrite the HDL testbench by Simulink...

[GerdW]

Hi,

so you have a working solution using MathWorks tools: why do you want/need to port all this to LabVIEW?

NI LabVIEW supports NI hardware, and you can create software using NI software tools for this  NI hardware...

[MrMYH]

Hello GerdW,

The design (A) for the NI board (A) is different from the design (B) for the board (B) supporting Simulink. The board (B) lacks some hardware units in the board (A), so I can't port the design (A) on it. The design (A) is ported from a cell-based flow ASIC.

[David-A]

I don't know if all FPGA boards support co-simulation, but I know most of the FlexRIO boards do.

Cycle-Accurate Co-Simulation with Mentor Graphics ModelSim

http://www.ni.com/tutorial/11574/en/

That white paper should get you started with co-simulation. Personally I prefer to write labview test benches for labview code and vhdl test benches for vhdl. But I suppose for someone like yourself that wants to reuse an existing testbench the co-simulation could be a good option. 

[MrMYH]

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@David-A wrote:

I don't know if all FPGA boards support co-simulation, but I know most of the FlexRIO boards do.

Cycle-Accurate Co-Simulation with Mentor Graphics ModelSim

http://www.ni.com/tutorial/11574/en/

That white paper should get you started with co-simulation. Personally I prefer to write labview test benches for labview code and vhdl test benches for vhdl. But I suppose for someone like yourself that wants to reuse an existing testbench the co-simulation could be a good option. 

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Thanks, David-A. I have known this thing. But it's different from what I want. The LabVIEW FPGA - ModelSim (or QuestaSim) cosimulation is just "simulation:" we can't run the testbench with QuestaSim and FPGA VI on the physical FPGA at the same time. We can run only the testbench with QuestaSim and the FPGA VI with QuestaSim at the same time.

For my board with Simulink support, I can run the testbench with ModelSim, and then the stimulus signals from testbench are passed from Simulink to the physical FPGA board.