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Perplexed by myRIO AO Sampling Rate

I am really confused about the myRIO Analog Out (AO) sampling rate. If anyone has any insights into the following please let me know.

  1. The max AO sampling rate is 345kSa/s according to the spec sheet. This value is aggregate for all AO channels.
  2. The FPGA clock is 40MHz, and I thought it served as the master clock. However, 345kSa/s does not have an integer number of 40MHz clock cycles in it. How is this possible?
  3. I made a simple test case VI and cannot think of what I am doing wrong, but the output frequencies from myRIO do not match up. They are off by a hertz or two.

Here is what I did:

  1. I made an 8 point block memory FPGA node. I set the values to 0,0,0,0,500,500,500,500 I16 integers.
  2. I put the memory in a loop to read and output the read operation to the AO.
  3. When I set the loop rate to 250kS, this is below 345kSa, I should have a square wave that has a frequency of 31.25kHz. But when I look at the data, I get 31.249kHz. See belowFreqOFF.png

 

If I change the update rate from 250kSa to 125kSa, then I get the right frequency, 15.625Hz, although the peak is slightly distorted.FreqON.png

 

 

 

Does it take a certain amount of cycles to update the analog out? What am I missing?

 

Thanks for your help.

 

Regards,

mcduff

 

 

PS Below is the simple test casesnip.png

 

 

 

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Message 1 of 11
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Maybe this is an answer.

 

Took 100s of data, did an FFT to get an accurate frequency. I got 31.24915kHz, instead of 31.25kHz. This implies the 40 MHz clock is running at 39.9989 MHz, this is greater than 10ppm. Is that value typical? (do not see in on spec sheet)

 

Cheers,

mcduff

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What if you used a timed while loop rather than a regular while loop with the delay timer in it?

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@RavensFan wrote:

What if you used a timed while loop rather than a regular while loop with the delay timer in it?


 

Excuse my ignorance/stupidity, but you can use a timed loop in FPGA? I thought they we only for SCTL in FPGA. I'm at home now without LabVIEW, but I will try tomorrow. Thanks.

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I know that I have.

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Writing the AO won't work in a timed loop, so the loop timer is the only option.

 

The 345kS/s rate is probably derived from the 40MHz clock using a method like this, and because there's no exact combination of multipliers and divisors it isn't an exact result. After running that VI the closest approximation is 345.0025k with a 0.000735% error, so I'm guessing that's what the DAC is actually running at. So this might account for the differences you're seeing.




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Unless otherwise stated, all code snippets and examples provided
by me are "as is", and are free to use and modify without attribution.
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@MichaelBalzer wrote:

Writing the AO won't work in a timed loop, so the loop timer is the only option.

 

 


You might be right, and I was mistaken.  I did use a timed loop in my FPGA code, but it was just to maintain an onboard counter based off the 40 MHz clock.  I don't know if it was effectively a single cycle timed loop or not.  My other loops in the code, including the one outputting analog data, were regular while loops and used the blue "metronome" to do waits based on the 40 MHz base clock.

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I think you're going to get some issues using the delay like that. Outputting to AO takes some finite amount of time, so with the sequence structure you'll be waiting 8 µs, then [AO write time], then looping. You're guaranteed to get something slower than your desired loop rate. It may not be significant (I don't know how many clock cycles it takes to perform an AO) but it may be worth looking into.

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@MichaelBalzer wrote:


Thanks for the link, quite honestly I am too stupid to know how to utilize it. I have tried creating derived clocks and the multiplier and divisor is fixed, I cannot change it.

 

Anyway, tried a bunch of different things, made a SCTL at 40MHz, that would generate an occurrence that I tried to use to trigger AO at a lower rate, but still my frequency was off.

 

I went back to my original thought, the 40MHz clock in the FPGA is off, that is, not really 40MHz. Luckily I have 2 additional myRIOs in a box to test. The first replacement gave the correct frequency with my original simple program. See below.FreqON.png

 

 

The peak is still not symmetric, but better than before.

 

If anyone from NI is reading this, what is your return policy?? Smiley Wink Where are the clock specs for the FPGA?

 

Thanks for everybody's help and advice, I could have saved everybody's time and effort if I just tried a different myRIO earlier.

 

Cheers,

mcduff

 

EDIT: Just did a 10s FFT got 31.2498kHz instead of 31.250kHz, only off by 0.2Hz, instead of ~1Hz.

 

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@BertMcMahan wrote:

I think you're going to get some issues using the delay like that. Outputting to AO takes some finite amount of time, so with the sequence structure you'll be waiting 8 µs, then [AO write time], then looping. You're guaranteed to get something slower than your desired loop rate. It may not be significant (I don't know how many clock cycles it takes to perform an AO) but it may be worth looking into.


Writing to the AO will take some time but the Loop Timer function should handle that, just so long as the entire loop execution takes no longer than 8µs. For example if the AO write takes 1µs the loop timer should only wait 7µs, keeping the loop running at the correct rate.




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Unless otherwise stated, all code snippets and examples provided
by me are "as is", and are free to use and modify without attribution.
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