My application is this: Calculate a serial bit pattern based on a VI. front
pannel, and then serially generate that pattern using a 32-HS board at 5 MHz.
An initial problem was that the VI can't generate the bit pattern that fast so
it cycliclly generates bit patterns as fast as it can and then stores it in a
buffer. After a while I trigger the board and (theoretically) the very
redundant pattern should be transmitted at 5 MHz. THe problem is that the
board doesn't seem to generate the pattern consistantly. About 40% of the time
there are sweep data replacements or missing data, or data from earlier in the
buffer repeated in the wrong place.
Has anyone accomplished successful pattern generated at 5 MHz? How was th
is
done if you had similar problems.
Please reply to the group,
I'm at a loss here at this even seems to stump the techs at NatInst.
Dave
