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Pass data sequentially to FPGA from a file being read

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Pass data sequentially to FPGA from a file being read

Dear all,

I am a new user of the Labview FPGA module, and I need your help. 

 

I have a huge file in my computer and I want to process it in my FPGA module. I have a VI to split into little files at first, but in order to pass it to my FPGA I don't know how. My idea is to create two blocks of memory in the FPGA module in order to have a Ping-pong structure, so while the second memory is being written the first memory has been read and the data is being processed.

The first problem is to pass this data to my blocks (is in text format and the FPGA does not accept it).

The second problem is that I do not know if wiring like it is done will work. Can you help me wiring it? I do not know if the data I should wire in the host to the read method will go directly to the data elements in the FPGA VI.

 

The memories created are of 64MB each one. I am working with FlexRio.

Thanks in advance.

King Regards,
Miguel.

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Accepted by topic author MiguelIrusta
05-03-2016 11:22 PM

Re: Pass data sequentially to FPGA from a file being read

What you want to do is create a DMA FIFO to send the data down to the FPGA.  Make the data type of the DMA a U8.  So on the host side, you just read your data from the file, use the String To Byte Array, and write to the DMA FIFO.  On the FPGA side, you just read the DMA FIFO inside of a FOR loop to make your array and then process it.  You might need to use another DMA FIFO to send the processed data back to the host computer.


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Re: Pass data sequentially to FPGA from a file being read

Thank you for your quick response,

Putting the FIFO in the host side and doing what you told me I cannot wire the data to the writting method of the FIFO...The error tells me that one is type 1-D array of unsigned byte, and the other type of the sink is void. Am I doing well?

Thanks again.


Kind regards, 
Miguel.

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Re: Pass data sequentially to FPGA from a file being read

That sounds like you did not configure the DMA FIFO for the FPGA.


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