PXie 7976 Clock generation

[bchang32]

Hello,

I am trying to use my flexRio to generate essentially an 80MHz clock. I created multiple versions to test and try to find the best clock.

I tried creating a clip as well as just a vi. For some reason, both generate an 80 MHz clock +/- .4MHz, but from looking at the datasheet, it should be able to generate a much better 80MHz signal.

My vhdl code is essentially this where count_M80 is a counter from 0 to M80, M80 is 0 to 1 (since my clock is 160MHz and with 50% duty cycle, 160/80*.5 = 1), and register_m80 is just a std logic and connected to my output.

	begin
		if rising_edge(clock) then
			if count_M80 = M80-1 then  
				register_M80 <= not register_M80;
				count_M80 <= 0;
			else
				count_M80 <= count_M80+1;
			end if;
		end if;
	end process tutorial;

 I tried the below to generate an 80MHz clock too by having the below in a 160MHz timed loop.

Shouldn't my clock output be a lot more stable? I have the clock connected to PXIe_DstarC and have a ni-sync vi to measure it.

[RavensFan]

It looks like your are using a NAND with a True to toggle the boolean.

Wouldn't it make more sense to just use a NOT?

[bchang32]

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@RavensFan wrote:

Wouldn't it make more sense to just use a NOT?

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It makes no difference. I have one version where I'm using a NOT gate and its just as volatile/unstable. I just didn't want to post essentially the same picture but with a different gate. My apologies.

[Terry_ALE]

Will this clock be interfaced with an I/O pin?

Asking because I rarely see such an implementation in LabVIEW FPGA since we typically derive clocks from the base clock(s).

[bchang32]

Update, Ive even tried all these to get essentially the same result

https://forums.ni.com/t5/Example-Code/Export-a-Clock-Signal-on-FPGA-Device/ta-p/3530075?profile.lang...

[bchang32]

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@Terry_ALE wrote:

Will this clock be interfaced with an I/O pin?

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Ideally this would be sent to the DStarC line and then outputted through a timing card.

[Terry_ALE]

That's an older (2010) document; I'd look for something more recent.

It is for DAQ cards but this may help: https://www.ni.com/en-us/support/documentation/supplemental/10/synchronization-explained.html

[bchang32]

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@Terry_ALE wrote:

That's an older (2010) document; I'd look for something more recent.

It is for DAQ cards but this may help: https://www.ni.com/en-us/support/documentation/supplemental/10/synchronization-explained.html

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So I believe I am doing what they recommend (Using the DStarC lines since im going from FPGA to timing card which is considered the best). It says I should expect about <500 ps of skew, but when I'm measuring it, im off by like 400 KHz which doesnt seem to make sense, unless its potentially from the ni-sync measure frequency accuracy? I've used the measure frequency vi prior and it was pretty accurate prior. I don't imagine the DStarC line to be that noisy or cause that much jitter?

[Terry_ALE]

Not sure what else to recommend.  May be good to reach out directly to NI support.