PXIe_CLK100

[bchang32]

Hello,

I am trying to access the PXIe_CLK100 like in this post 

https://forums.ni.com/t5/LabVIEW/Not-able-to-choose-PXIe-clk100-on-chassis-devices/td-p/3929179?prof...

and http://www.ni.com/product-documentation/11369/en/ (figure 😎.

However, using ni-DAQmx, I cant even get those properties of DAQmx Timing to show up. I try to browse and when I try to add it, nothing happens. No matter what value I click under select properties, nothing carries over.

I'm not sure if I'm supposed to be using DAQmx compared to NI-Sync, so did this change relatively recently (like less than a month ago since the first posts was in May)? How does one access the notorious PXI_CLK100? It seems like no one is able to?

[croohcifer]

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@bchang32 wrote:

I'm not sure if I'm supposed to be using DAQmx compared to NI-Sync, so did this change relatively recently (like less than a month ago since the first posts was in May)? How does one access the notorious PXI_CLK100? It seems like no one is able to?

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The drivers you use depend on what is in your chassis.  PXI_Clk100 is just a 100 MHz clock that is ALWAYS on the back of a PXIe chassis regardless of whether a timing card is present.  For a DAQ device to use PXIe_Clk100 as its reference, first you need to verify that your DAQ device CAN use it (check the device specs) as a reference clock.  You then need use a DAQmx Timing Property Node to set the RefClk source to "PXIe_Clk100" and the RefClk rate to 100 M on all open tasks on that DAQ card. 

This will explain why you can't see all of the properties:

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z000000kFGaSAM&l=en-US

As to the timing card, if you want PXI_Clk10 and PXIe_Clk100 to inherit the OCXO timing accuracy provided by your 6674T, use the NI-Sync API to connect "Oscillator" to "PXI_Clk10_In".  That will tell the backplane to PLL its backplane 10 and 100 MHz reference clocks to the timing card's high precision 10 MHz oscillator.  Both 10 and 100 MHz clocks will then inherit that 10 MHz clock's accuracy because both backplane clock are PLL'd to the timing card's oscillator.

Remember that just because you route the timing card's better oscillator to the backplane's PLL circuit doesn't mean that all devices in the chassis CAN or ARE using these clocks.  You have to check the modules' spec sheets to make sure they can use the clocks and you have to make the specific NI-DAQmx or NI-SCOPE or NI-FGEN or whatever APIs (depending on the module) to actually force the module to use the backplane reference clock.  A module will usually only ever support either the 10 MHz OR the 100 MHz reference clock, not both.  If you have one of each kind of card and they each reference one of the backplane clocks, they won't drift from one another because the 10 and 100 MHz backplane clocks are phase locked to one another.

[bchang32]

Thank you for all the info and help (especially on both threads).

So I've tried using the property node but it appears the "select filter" tab doesnt appear (I'll have to double check monday). I believe the 6674T can take in the PLK_CLK100 (according to page 10 of the datasheet). I'm using labview 2019, so i hope that isnt the cause?

Also my chassis is the 1095, so does that mean I should use both? When I did NI_Sync, the 100 MHz clock doesnt appear as an option too when the 6674T should be able to handle it. From reading the datasheet, the 10 MHz clock is made by doing a divide by 10 on the 100MHz clock. If I want both to be synced, shouldnt it be the opposite (have the oscillator synced to the 100MHz?).

Thanks once again!

[croohcifer]

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So I've tried using the property node but it appears the "select filter" tab doesnt appear (I'll have to double check monday).

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 No comment.  It appears on my machine, so please double check and provide screenshots if you find that it's really not there.

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I believe the 6674T can take in the PLK_CLK100 (according to page 10 of the datasheet). 

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"Take in" is not descriptive.  On page 10, the specs are saying that the 6674T can use PXIe_Clk100 from the backplane as a reference source for clock generation using DDS.  This allows you to generate clocks of very specific frequency for very niche applications.  (I rarely run into use cases for this.)  This use-case has nothing to do with routing a 100 MHz clock to the backplane through the timing card's PXI_Clk10_In terminal, which isn't possible.

I'm using labview 2019, so i hope that isnt the cause?

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Your LabVIEW version has nothing to do with any of this.

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Also my chassis is the 1095, so does that mean I should use both? When I did NI_Sync, the 100 MHz clock doesnt appear as an option too when the 6674T should be able to handle it. 

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Again, "use both" and "handle it" are not descriptive enough.  The 6674T can use different signals for different operations.  Page 25 goes into this in detail (http://www.ni.com/pdf/manuals/377485a.pdf) in terms of routing capability.  Again, to drive the point home, the table on page 25 shows that the only two things that can be routed to PXI_Clk10_In are "OCXO" (the 6674T's high accuracy 10 MHz oscillator) or "CLK_IN".  Connecting "CLK_IN" to "PXI_CLK_10_IN" doesn't guarantee that the chassis will PLL PXI_Clk10 and PXIe_Clk100 to it.  The clock you provide must actually be in the frequency range (10 MHz +/- 25 ppm) as discussed previously for the chassis to use it. 

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From reading the datasheet, the 10 MHz clock is made by doing a divide by 10 on the 100MHz clock. If I want both to be synced, shouldnt it be the opposite (have the oscillator synced to the 100MHz?).

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I should have been clearer on this point before.  When it comes to clocking, things get really specific really quickly.  The chassis has a 100 MHz oscillator running at all times that produces a clock signal we call PXIe_Clk100.  It also has a PXI_Clk10 signal, which is divided down from PXIe_Clk100.  I'm not sure if the divide down is a strict part of the PXIe spec, but you could check since the spec is public.  In theory, I suppose PXI_Clk10 could be PLL'd to PXIe_Clk100 or vice versa.  Thankfully we don't need to know exactly how it works because the documentation tells us what we need to know:

1. We can only provide a 10 MHz clock to the backplane.

2.  Both 10 and 100 MHz backplane clocks inherit their accuracy from the provided external 10 MHz clock.

That said, assuming the clocking architecture specified in the 1095 user manual, I'll clarify what I wrote before.  Previously I stated that the chassis will "PLL its backplane 10 and 100 MHz reference clocks" to the external clock.  Another way to state it is that: "The chassis will PLL PXIe_Clk100 to the external 10 MHz clock.  Because PXI_Clk10 is derived from PXIe_Clk100, both backplane clocks inherit the accuracy of the external clock."  PLL circuits use multipliers and dividers to PLL clocks of dissimilar frequencies and can have multiple outputs with different frequencies, so the fact that the 10 MHz external clock is multiplied by some factor (e.g., 10) to get PXIe_Clk100 and then divided by 10 to get PXI_Clk10 doesn't mean that that divide operation happens outside of the PLL circuit.  It could well happen in the PLL circuit, in which case my previous statement is still accurate.  It's all just semantics at that point.

Why distribute a 10 MHz clock instead of 100 MHz externally?  Because 10 MHz is a ubiquitous instrument synchronization frequency standard shared across many platforms and box instruments, and it's way easier from a signal integrity perspective to distribute lower frequency signals than higher ones.