I would like to use 3 PXI-6713 analog output with a buffer ans synchro it with a frequency signal on PXI-6713 update port. I made an exemple with CVI/labwindows but I would realize it with labview 6.1. Have you got some sample ? Thanks for your help
It does not appear that any examples with this exact functionality are available, but you should be able to use the Cont Generation - ExtClk.vi example as the foundation of your application. The master PXI-6713 will use the external clock signal as its update clock. Additionally, you will need to use Route Signal.vi to route both the mater PXI-6713's AO Start Trigger and AO Update signals to the RTSI (PXI Trigger) bus. The two slave PXI-6713s will both use these two RTSI lines as their start trigger (AO Trigger and Gate Config.vi) and update clock (AO Clock Config.vi), respectively.