Excuse the convoluted wording of my original post. I'll try to explain it a bit better. I meant that the timing signal needs to have 50ns resolution, as in, it needs to switch logic levels within 100ns (10MHz). For the first 21 100ns cycles, it needs to oscillate in sync with the 10MHz clock, then it needs to stay at logical hi for 19. My data is being clocked out by the 10MHz clock. The waveform data will consist of 21 cycles of data and 19 cycles of constant low. The timing signal must accompany this. It would be nice if I could store both signals alongside each other and output them in parallel but I will only have 100ns resolution at 10MHz. I was wondering if I could run a simple case statement (if <21, output clock, if >21, go to hi) while the board is
clocking out the waveform data that's stored in the buffer.