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Output and input analoge with FIFO

Hi All


I need to create a code in FPGA that at the same time create:

- 4 analogue output with NI 9263 (1 that can change in sin, square and so on with variable voltage and frequency, and 3 static voltage) 

- Analogue input with a high-frequency resolution of 16 channels.

- There will be also digital in the future

 I have attached all the VI created.

However, I have created the FIFO for sending and receiving the analogue data and to be sure about the quality of the result I have attached to the system a real oscilloscope.

When I am running the FPGA program there is a response delay in the analogue input given but the analogue output (I have attached the picture of the issues).

I am struggling to understand why this issue is happening, and why the input time in (usec) doesn’t work as expected. Why the wave is only between 20 and 40 samples and not among all the data?

All the best





Host to Target FIFO.JPG

Target To Host FIFO.JPG



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Hi Francesco, 

I am wondering why you need the wait function in the FPGA code. I think the delay that you have mentioned is connected with that wait function, if you have it in your code there exactly will be some delay. Also, I notice that you have many coercion dots in the Host part, which is causing some delay through the conversion. Try to remove the wait functions and correct coercion dots, after that your program will work better then now.




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