You have the module in the project set to calibrated output mode where the offset and span for the ADC are compensated in the IO node. The other option is to right click the module in the project and set the output to raw. This will require you to read the offset and span coeff's stored on the 9237 module and compensate on the host side.
The calibrated mode is simply outputting a FXP value with enough resolution to represent the voltage value on the ADC, which is quite handy.
FXP is worlds more computationally efficient than a floating point data type. On the FPGA, you can only have SGL as it is. Generally speaking, you want to get to a FXP representation to optimize your code.
Why are you concerned that it's FXP? Is there any reason you want to avoid this?