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Ni 6587 example serial generation - export clock

Question about example:

In the host VI, I see contants being passed to the FPGA  via a write control, the same I/O port oBoard_Clock_Write 3 times with a F, T and F why write to the same Io 3 times within 1 occurance of the IO node?

This same thing happens with the Xpoint_Switch_Write I/.

See attached

 

What effect does that have on FPGA execution?

 

 

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Hi lsutiger,

 

The I/O nodes reference functions on the FPGA VI that are responsible for configuration of the clocks on the module and the card. The false, true, false constants are sent through as a part of the configuration. Although I haven't tried it myself, you could try just sending a false constant through, although I would guess that the difference in FPGA execution would be unnoticeable as passing constants typically requires much less overhead than sending a control value. This KB shows a bit more behind why the code is done this way.

 

Tim W.

Applications Engineering

National Instruments

http://www.ni.com/support 

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The fundamental question is how does the code arbritrate the occurance of 3 entries. What does the FPGA do with the signal in the background?

If the FPGA actually rolls through the different inputs on successive clock cycles (the 1st occurance on clock cycle 1, 2nd occurance on clock cycle 2 and the 3rd occurance on clock cycle 3) this feature may be usefull for other problems that i am trying to solve

 

 

I'll try the example with the other occurances deleted and see what happens

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After talking with one of our product support engineers, I have a bit more info on what is actually going on here. Basically the I/O node executes in order from top to bottom. Sending a false, true, false is meant to force a rising and falling edge to clock in the signal. When working in single-cycle timed loops the I/O node execution still goes from top to bottom in one clock cycle. For this particular example, this is important because Onboard_Clock_Write will latch the value of Onboard_Clock_Write_Data on a rising edge transition. This is detailed a bit more in the LabVIEW help file (search for 6587) NI 6587 Basic Connector CLIP Reference. Sorry about any confustion there. Sending a constant single false through will not work because the program is expecting a rising edge.

 

Tim W.

Applications Engineering

National Instruments

http://www.ni.com/support 

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