Network Stream grinding to a halt after ~1min

[KieranW]

Hi, I hope I can find some advice for this issue as forum searches have turned up nothing that sounds like this.

Using a cRIO-9030, with LabVIEW 2019 and associated Real-time and FPGA modules.

I have a FIFO removing data from an FPGA, which I then network stream to a PC in order to save it to a file.

Everything previously has been running smoothly, but recently the Network stream seems to grind to a halt after ~1000-2000 items have been read. It doesn't disconnect, but it slows to barely reading one value every few seconds,  then eventually stops, despite the writer loop still writing data at several times a second.

As far as I can tell from probing a network stream node, the network stream is not building up excess data. Any suggestions what could be causing this? I've attached below the writer loops, the reader creation and reader loop.

[raphschru]

Just by looking at your pictures is not easy, but there are already several things I find a bit strange:

 - On your 3 parallel FPGA FIFO Reads, it looks like you have wired "0" to "Number of Elements", preventing any data to be actually read.

Make sure you have wired "Elements Remaining" from the inital read instead.

 - Even if it is correctly wired, you use the number of elements present in 1 FIFO ("FPGA to RT data 1") to read from 2 other FIFOs ("FPGA to RT data 2" and "FPGA to RT adresses").

Are you sure all 3 FIFOs always have the same amount of data ?

If one FIFO has less, it will give an empty array.

 - On reader creation, have you tried to change the allocation mode to "allocate as needed" ?

May not be this, but why use 2 different strategies for the same data...

 - I would also try to just remove the "Write to Text File" function to see if this is the culprit.

If the writing buffer somehow is full, you may want to add a "Flush File" to ensure the buffer is regularly emptied.

If the writing is too slow, I would consider using TDMS files instead.

Good luck !

[KieranW]

Thanks for replying.

After a quick check;

- It is connected to the "Elements remaining" output, for some reason the wire is just hidden behind the FIFO Read

- The three FIFOS should all receive the same amount of data, the FPGA is reading this data from an IO Node and should be sending it to the three FIFOs

- I think I might have changed the allocation mode whilst attempting to debug this but I can't honestly remember, I'll have a look and see if this makes a difference

- I'll see if changing to TDMS files makes a difference too.