NI PXIe-7972R + NI 1483 cannot compile w/ Xilinx Vivado 2013.4

[volume2]

Hi, 

I'm using LabView 2014 and trying to connect NI PXIe-7972R + NI 1483 adapter to capture image from camera-link pco.edge camera. After install the driver of the PXIe-7972R, I try to compile the example target with "10-Tap 8 Bit Camera.lvproj" project. The PXIe-7965(with Virtex-5 FPGA) can compile off-line successful. However, when I try to compile the PXIe-7976R and PXIe-7972R FPGA target (both have Kintex 7 FPGA) with Vivado 2013.4, it doesn't work as attachment figure. I'm pretty sure the Vivado 2013.4 can support the PXIe-7976R and PXIe-7972R target (http://www.ni.com/product-documentation/53056/zht/), and I already install this compiler.

It seems Kintex-7 FPGA compiler have some problem, but I'm not sure.

The attachment are my error figure and code from example, thanks.

[altenbach]

Almost looks like windows 10. I think that's only works with the newest compiler.

[volume2]

Yes, my OS is win10. But it doesn't work. I'm so frustrated.

[altenbach · Accepted solution]

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@volume2 wrote:

Yes, my OS is win10. But it doesn't work. I'm so frustrated.

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Exactly! Windows 10 does not support your compile tools.

Follow the flowchart here to decide what to do.

(see also this thread)

[volume2]

Seems cloud compilation is doable. Thank you very much.

[tiba.shokatpour@gmail.com]

Hi

I have a simple FPGA program that compiles in cRIO without any problems, but I want to use the FPGA program on the NI 9144 EtherCAT Expansion Chassis in FPGA mode to NI PXIe 8135 (Code file attached). As you know there are some differences between programming the local FPGA and the FPGA for EtherCAT RIO, that must be used user-defined I/O variables (this paper).

For Compiling I did step by step as this paper said, we get successful processes, but after file generation complete we have an error (that attached). It shows that the file can not run in chassis. 

Please help me.

Regards. 

[RMowatt]

This thread is already marked as solved.  No one is going to come in to view and help.  I suggest making a new post for your specific problem

[volume2]

Hi,

I haven't use PXIe 8135 before. I think might be you can click "investigate timing violation" to see where is the error from. For FPGA/Host data transfer, I usually utilize FIFO for fast data transfer. 

Best,

Yong

[tiba.shokatpour@gmail.com]

Hi

I found the solution for Timing Violation Errors, In this link ( section 4)

The following are suggestions for improving timing in your FPGA code:

• Adjust the build settings to optimize for performance (Note: this may increase compilation times, and may result in area trade-offs).
• Optimize your code. Try the following best practices and optimization techniques within your LabVIEW FPGA code.
  • Reduce the amount of logic in the VI
  • Add pipelining to increase parallelism
  • Use Timed Loops instead of other loops
  • Change arbitration settings

I just use Timed Loops instead of other loops, so the compilation runs successfully.  

Regards.

[volume2]

Congrats, thanks for your sharing.

Best,

Yong