When we use IO clock instead of Onboard clock it significantly reduces the amount of FPGA resources we can compile. Why is that ? and how can we solve it ?
When you say that it reduces the amound of FPGA resources you can compile, do you mean that the device utilization is increased when using the IO module clock, or does it fail timing easier when you use the IO module clock? Also, what adapter module are you compiling for?
I mean that the device utilization is increased significantly, we use NI 5781 Transceiver for PXIe-7962R.