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NI PXIe-7962R io clock for timed single cycle timed loop

When we use IO clock instead of Onboard clock it significantly reduces the amount of  FPGA resources we can compile. Why is that ? and how can we solve it ? 

 

 

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Message 11 of 13
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Hi Omribarlev,

 

When you say that it reduces the amound of FPGA resources you can compile, do you mean that the device utilization is increased when using the IO module clock, or does it fail timing easier when you use the IO module clock? Also, what adapter module are you compiling for?

 

Thanks,

Kyle

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Message 12 of 13
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Hi Kyle,

 

I mean that the device utilization is increased significantly, we use NI 5781 Transceiver for PXIe-7962R.

 

Thanks!

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Message 13 of 13
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