I am trying to read the CAN signals from a vehicle using the CAN Signals Receive (Host) and CAN Signals Receive (FPGA) example vi's. I am using Labview 2013 with the FPGA Module and my hardware consists of a Compact RIO NI 9146 Expansion chassis with an NI 9853 High Speed CAN Module. The FPGA vi seems to be working like it is supposed to, the host vi seems to be having a problem converting the frames to a signal. In the host vi I click the arrow on the "signals list" and choose the "browse for database" option and then upload the database for the vehicle. When I run the vi's, though, I don't get any values other than zero on the "CAN Signal" indicator. Several of the channels will show the value of the offset in the database, but several other channels which have offsets still show zero.
When I go into the host vi block diagram and open up the NI XNET sub vi that is supposed to "Convert the array of U32 to Signals" it opens the front panel for the XNET Convert (Frame Raw to Signal).vi Front Panel. While running the vi, the "frame data" indicator is displaying the values coming in on the CAN bus but I don't get anything other than zero (or the offset value of several of the channels) displayed in the "signal data" indicator. After opening the block diagram of the XNET Convert vi there is a note stating not to change anything.
Is anyone able to help me figure out why I am not getting any signal data?
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It looks like you pulled your FPGA VI and host VI from the Example Finder but made a few modifications. In the host VI, it is important to wire the Resource Name terminal of the Open FPGA VI Reference VI so your host VI can locate the FPGA. The Resource Name should be of the form: rio://<IP Address>/RIO0. If you add an I/O constant, you should be able to browse to the correct resource name.
Also, why did you switch the wiring for the input to the XNET Convert VI? The example uses the Flatten To String VI and the String to Byte Array VI. Did the original wiring configuration also return all zeros for the CAN signal?
Thank you for the response, and I must apologize for not explaining the two problems you found in my first post. The Open FPGA VI Reference VI is wired and locates the FPGA, but the FPGA is connected through a local link on a different computer. That computer does not have internet access so I copied the VI's and opened them on my office computer which has internet access but is not connected to the FPGA, which (I believe) is why the Open FPGA VI Reference VI appears unwired.
The original wiring configuration in the example also returned all zeros for the CAN signal. I was experimenting with a few different configurations, all of them returned all zeros for the CAN signal. I apologize for not switching it back to the original wiring before I posted.
Thank you for the additional information. I am a little confused as to how your system is setup (computer, network, cRIO). Can you explain this further? Generally when you use an Open FPGA VI Reference VI to run a remote FPGA VI, you need to specify the resource name to make sure the FPGA is found and run correctly.
Also, you said you believe the FPGA portion of the application is functioning as expected. Can you explain this a little more? What tests did you do to confirm this?
To further debug, can you add indicators in the Host VI to watch the values of data and the array of data values? I am curious to see what these values are before they go into the Covert VI. It would also be worthwhile to run the Host VI in highlight execution to be sure we aren’t getting any errors and to confirm that it is flowing as expected.
The cRIO system is connected directly to the computer via an ethernet cable. The cRIO system and host computer are currently being used on a vehicle dyno to monitor the vehicle speed and adjust the throttle so the vehicle follows a speed trace. We have been using the cRIO system for this purpose for several months now. We would like to be able to monitor CAN messages with this program as well so on days when the dyno is not in use I have been working on this CAN example so that after I get it communicating correctly I can add it to the main dyno program.
I have attached several screenshots of the program. Two of the screenshots are of the Host and FPGA VI's with the vehicle off so there are no messages being broadcast on the CAN bus. Several of the other screenshots the vehicle is on so the CAN bus is active. The CAN_VBR channel is battery voltage and should be reading 12.6, 4 is the offset value of this channel in the CAN database. The CAN_TCO is coolant temperature and should read 140, this channel does not have an offset value. An interesting note, when I ran the program for the first time after downloading it to the 9146 chassis the value of CAN_VBR was 9.16. Every time I stopped the program and ran it again the value remained at 4.
Last is a screenshot of the Host VI block diagram running in highlight execution mode. I moved things around so it would all fit on one screenshot but I didn't notice until now that the String to Byte Array object is covered by the value of the Flatten to String object.
Hopefully this sheds some light on why things aren't working correctly. I did notice that the FIFO overflow indicator is on constantly. Could this be a source of the problem? Even if the buffer was full shouldn't the channels still read correctly? The NI 9853 CAN module that we are using is intended for the ISO 11898 standard. Does it also support the ISO 15765 that we currently use?
Based on the screenshots, it looks like you are getting some data on the CAN bus. How do you have the signals setup in your database?
The FIFO overflow indicator could definitely be part of the problem. If the FIFO is full when the FPGA VI tries to write a new value to it, the value gets thrown out. Because this VI relies on having 6 consecutive samples so it can reconstruct the frame, losing any of those values would mess with the data values of the frame. The documentation for this example says that it is recommended that the Host VI be run on a Real Time target because rather than a Host connected to the FPGA VI Ethernet: “Due to the latency in the remote server connection between a host VI running on Windows and an FPGA VI connected via ethernet, it is recommended to run the host VI on a RT target.” Since you are using an ethernetRIO, this could explain why the FIFO is constantly overflowing. We may be able to work around this by using the CAN cluster format instead of the array of U32s. You will need to use a Read/Write control for this, which means we will only get the latest value, not every frame. You could then unbundle the cluster in the Host VI and process the data.
For this particular application it is not necessry to capture every frame. Capturing only the latest value should work just fine (however I will keep the RT target in mind for future projects). Could you possibly point me towards an example of using the CAN cluster format, and how to process the data in the Host VI?
Did you double check the way the signals are setup in your database? Though it seems like the issue may be due to the FIFO overflowing, it’s a good idea to make sure the database is setup correctly before restructuring the code.
The CAN Basic project in the Example Finder shows using the cluster format to do a loopback test. The two format options for the I/O node (cluster and array of U32’s) are explained further in the article linked below:
I created a VI that converts the Cluster into an array of U32’s. On the FPGA side, you wire the I/O node to an indicator. On the Host side, you use a Read/Write Control to read the value of the indicator. You can then use the attached VI to convert the value to an array of U32’s and wire that array into the Flatten to String VI and reuse the remainder of the Host VI (picture attached). With this method, there isn’t any handshaking between the Host VI and the FPGA VI so you will miss frames.
Thank you for all of the help. The suggestions and VI that you sent worked and I was able to get the CAN communication working.