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NI 9242 wrong sample rate

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Dear community, I have a small problem with NI 9242 module. I am using it in my test bed to read the frequency of the grid voltage. In my design I have used an example provided by NI regarding the NI 9242 module. I am using the block "Build waveform" to build the signal with the help of the data acquired from FIFO. For "Build waveform" I use a "dt" value of (1/50000), because my module is working on frame rate of 50 kS/s. However, if I use the "dt" of 1/50000 I get the wrong value of frequency of the grid (which is 50 Hz for sure). To receive the correct value I use "dt" of 31250. Why is this happening? Any clues?

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Hi Sergii,

 

the datasheet for NI9242 specifies sample rates of 50kS/s, 25kS/s and smaller…

 

When your software generates data with 31.25kS/s then the problem is in your software.

Either you debug on your own - or you need to attach your VI(s)…

Best regards,
GerdW

using LV2011SP1 + LV2017 (+LV2020 sometimes) on Win10+cRIO
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The thing is, there is no possibility to choose the frame rate of the module to be 31.25 kS/s. I have attached the VIs both for rFPGA and Host side. Thanks in advance. 

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Solution
Accepted by topic author Sergii_Lev

Hi Sergii,

 

what's the loop rate of the outer while loop in your FPGA VI?

Why don't you put each module in its own loop? Some modules are slower than others and might slow down the whole loop!

What kind of wait did you program in this loop? How long is this "100" with a coercion dot?

 

And both VIs are WAY TOO BIG! Using 12 FullHD screens for a block diagram is ridiculous!

Best regards,
GerdW

using LV2011SP1 + LV2017 (+LV2020 sometimes) on Win10+cRIO
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Hi GerdW,

 

The loop rate is 0 us, that 100 us was in the old version of the code. Does that mean that all C modules run at their maximum speed, right? Should I use any time counter, or just delete it?

 

I will put each module in its own loop, that is a very valuable comment, thank you.

 

Regarding huge diagram - yeah, I am using a big screen, but first thing is that it was my first project in LabVIEW, and I didn't want to make a lot of subVIs, in order to adjust the code later. 

 

 

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Hi Sergii,

 

Does that mean that all C modules run at their maximum speed, right?

No. Some modules can be configured in their right-click properties…

 

Should I use any time counter, or just delete it?

To have an accurate loop timing you should use a wait function…

 

Regarding huge diagram - yeah, I am using a big screen

But not as big as your BD are! Even on a 4K screen you need to scroll!

 

I didn't want to make a lot of subVIs, in order to adjust the code later.

Well, as you run into problems you can "adjust" your code now! 😄

Best regards,
GerdW

using LV2011SP1 + LV2017 (+LV2020 sometimes) on Win10+cRIO
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Works perfect now, thank you very much! What I also noticed is that compilation process of FPGA code was much faster, almost 3 times faster!

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