I am trying to route a non 10MHz or 100MHz signal from CLKIN to the PXIe-1095 backplane and then back out through CLKOUT. For verification purposes, I have CLKOUT to a oscilloscope. Using NI-Sync, when I connect terminals directly from CLKIN to CLKOUT, it outputs the waveform, but when I have it go to PXI-CLK10_IN and then have PXI_CLK10 to CLKOUT, its stuck at a 10 MHz clock. Does anyone know why? Attached are my POC codes.
Here's an example of my setup.
Function Generator --> 6674T --> CLKIN --> PXI_CLK10_IN --> PXI-1095 --> PXI_CLK10 --> CLKOUT --> Oscilloscope
Ive tried doing this https://forums.ni.com/t5/LabVIEW/PXIe-6674T-sync-to-backplane/m-p/3921091?profile.language=en to no success (it wont even run. it says something about invalid terminal).
Solved! Go to Solution.
In the future, please questions about timing cards here: https://forums.ni.com/t5/Counter-Timer/bd-p/40
The PXI backplane can ONLY accept 10 MHz clocks from external sources. (This is a hard requirement of the PXI specification and is true of all PXI chassis from NI or any other PXI-compliant vendor.) If you were to somehow get something other than a 10 MHz clock on the backplane traces feeding all of the devices in the chassis, you would likely see catastrophic failures since PXI-compliant devices are not generally designed or tested to operate on other reference clock frequencies from this backplane source.
More specifically, per the "External Clock Source" section of the 1095 spec doc, the clock you provide through the timing card or the SMA connector on the chassis must be 10 MHz +/- 25 ppm (i.e., 10 MHz +/- 250 Hz).
Per the footnote on page 8 on the spec 6674T specs (http://www.ni.com/pdf/manuals/377485a.pdf), the 10 MHz backplane clock isn't simply replaced with what you wire into it through the timing card. A PLL circuit in the chassis is used to synchronize an oscillator on the chassis backplane to the 10 MHz external clock you provide. (The 100 MHz backplane clock is also generated in this process to ensure that the two clocks don't drift with respect to one another.) This ensures 10 MHz phase continuity to all devices in the event that your external clock stops or is interrupted/glitchy/whatever so that you don't have catastrophic timing failures if the external clock were to suddenly disappear. If your provided 10 MHz clock is actually 9 MHz, the PLL on the backplane is likely not able to PLL to it (PLLs have specific tuning ranges, and this one's range is probably intentionally limited to the spec'd range to prevent out of spec clocks), so it ignores your input and uses the default 10 MHz clock that resides on the backplane.
What is your use case for wanting to replace the backplane 10 MHz reference with something other than 10 MHz? There are typically other ways (like individual device ref clock inputs or PXIe DStar lines) to provide exotic clock rates to individual modules in a chassis. These options are module-dependent (as are the supported clock rates - you generally can't just provide any rate you want), so you should consult the individual modules' user manuals and specifications to understand the capabilities.