Showing results for 
Search instead for 
Did you mean: 

NI 6587 ADC example - acquisition clock

I have some questions about this example.

It's a example for LVDS communication with ADC. There is something which I don't understand. In "NI 6587 Communicating with ADC (FPGA).vi",  "LVDS Input Reading and Configuration Loop". See the picture below:image.png

I think this clock should in rate and phase match the frame clock(FR). That means a complete frame will be acquired in one clock cycle. But the example said the clock for this SCTL should be configured from DCO signal:


My questions:

1. Clock rate can be changed to match FR, but how can we guarantee the clock phase is aligned with the data?

2. My ADCs sample rate is 100MHz. The FR is also 100MHz. Is there a problem that SCTL runs in such a clock rate?

0 Kudos
Message 1 of 1