Moving Average Filter

[crossrulz]

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@sammir wrote:

THanks for all the reply. But this code is working fine in simple Labview but not in Labview FPGA. So please if some one designed the moving avarage filter in labview FPGA so please let me know. Or post the result or answer so that can be useful for otheruser also.

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How is it not working?  What error are you getting?

[Ajaxy]

Hello\

Please check the attached pic.

And in place of array I wanted to connect the analog input from the FPGA for example two channels. So please suggest the solution.   

[WillD]

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@sammir wrote:

Hello\

Please check the attached pic.

And in place of array I wanted to connect the analog input from the FPGA for example two channels. So please suggest the solution.   

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Do you need to have a variable sample window? For FPGA programming it is better to pick a sample size at design time to save space.  The prior implementations I posted will work for static sample sizes.

You may be able to use the Xilinx RAM based shift register for a variable delay with the subtraction portion depending on what chasis you have.

[Ajaxy]

Yes I need to have variable sample window. So please can you attach your program VI so I can test it for my target. So I can see the result and what I am doing wrong 

I have cRIO 9082 Chassis with 8 slots.

[WillD]

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@sammir wrote:

Yes I need to have variable sample window. So please can you attach your program VI so I can test it for my target. So I can see the result and what I am doing wrong 

I have cRIO 9082 Chassis with 8 slots.

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This should work, although it is untested.  You can duplicate the Z-n blocks for more delay(sample size).  If you use powers of 2 for sample size you can use a bit shift to do the division and save space.  The average won't be valid for the first n samples.

Edit: Had the subtract inputs swapped.

[WillD]

I guess I ran out of edit time.

Actually the decrement on the input of the Z-n is unneeded, the function inludes the 1 sample latency.

I would replace the divide with a multiply by reciprocal.  With the reciprocal as a control loaded by the host system.

[Ajaxy]

Hello

I am agree with WillD but the problem is we can not use the other data type and FPGA only gives us output in the FXP format and processing the FXP data are bit complicated. Also I have tried your solution but for me its not useful but thanks fort the solution. If you have some idea then you can try the proposed example and see the result and let us know the solution. 

So with the fig you can more clear.

[crossrulz]

That variale delay node is an FPGA IP.  It can't run in a host.  On the host side, you are going to need to implement the array manipulation I performed in my proposed solution.

[Ajaxy]

Hello crossrulz

Where can I find your proposed solution.. 

[WillD]

Do you want to do the calculation on the FPGA or the Host?  FPGA has been mentioned numerous times, so I figured you needed it in the FPGA.

On the host there are many ways:

Pass your data as an array, size = sample size, use the Mean.vi

Pass your data into a loop and for each sample use the Mean-Pt-by-Pt.vi

Use the array method shown previously in this thread.