Labview NI-FPGA, generating N pulses at high frequency (1-5 MHz)

[constructionworker]

Hello everyone

I want to control the number and speed of pulses to be produced on the NI-FPGA through the NI-myrio application. But I want to do this at frequencies between 1 mhz-5mhz, so I need to use a timed loop. For loop cannot be used in timed loop, there is a way to do this without using a for loop ?

example is attached.

Any opinion given is worthy of respect.

[GerdW]

Hi worker,

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@constructionworker wrote:

But I want to do this at frequencies between 1 mhz-5mhz,

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In your message title you speak about "1MHz to 5MHz", but in the message you write about "1mhz to 5mhz": that is a difference of 10^9. (Did you learn about correct usage of SI units?)

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@constructionworker wrote:

But I want to do this at frequencies between 1 mhz-5mhz, so I need to use a timed loop. For loop cannot be used in timed loop, there is a way to do this without using a for loop ?

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Why do you need a "timed loop"? There is no "timed loop" on FPGA, but there is a SCTL instead…

You already use the correct timing function (LoopTimer): why do you want to use a different timing function? Do you know you can set LoopTimer to wait for pulses of the loop base frequency (most often 40MHz) instead of ms or µs?

Hint: when attaching RT/FPGA code it is recommended to also attach the lvproj file as that file contains all the definitions for your RT/FPGA target…

[constructionworker]

In your message title you speak about "1MHz to 5MHz", but in the message you write about "1mhz to 5mhz": that is a difference of 10^9. (Did you learn about correct usage of SI units?)

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First of all, thanks for your answer.
Mhz-MHz It may be a language problem. Sorry.

I want to use SCTL. My only question is how should I proceed as an alternative to for loop.
I tried a code like below, but I was still able to generate a maximum frequency of 500 khz.

RT-FPGA is already in lvproj.

I'm using a timed loop I can't set the frequency. I want to change the pulse rendering speed.

I am using a timed loop (SCTL) and cannot set the frequency. I want to change the pulse rendering speed.

A piece of code like below does what I want to do, but how can I change only the repeat rate. For example, I want to change from 1MHz to 4-5 MHz instantly. Is there a way to do this?

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[Bob_Schor]

Although I'm not generating pulses at such high frequencies (because my project doesn't require it), the way I do this is to have the FPGA deliver a single pulse, and have the RT code running in the myRIO generate (via a Timed Loop) the timing for generating the Pulses.  If memory serves, the myRIO's clock goes up to 1 MHz, so this might not be fast enough, in which case I would consider nested loops in the FPGA, the outer loop running (and counting "how many") from 1 MHz to 5 MHz and driving the inner loop that makes a single Pulse.

Bob Schor

[constructionworker]

Thank you for your answer.  Bob_Schor
I don't quite understand what you said. But I think you are talking about creating nested while loop in FPGA. But SCTL does not accept wait or similar timing in nested loops.
If I misunderstood, could you explain the situation a little bit?
Actually, 1 mhz frequency is enough for me, I was able to create a maximum frequency of 500 khz using a loop timer.

[natasftw]

Really, what you're looking to do here is send a pulse at some time.

If you have a 5MHz clock.  You'd send this every iteration of the SCTL to have that pulse go at 5MHz.  You'd send it every 5th iteration to get 1MHz.  You don't need any internal loops.  You just need logic to determine to send the pulse or not. 

What precision do you need for your frequencies? Also, how flexible is the choice within that range?

[Bob_Schor]

Oops -- I keep forgetting that FPGAs are Very Different (I've only been doing FPGA stuff a very few years).  Suppose you have an FPGA While Loop inside of which is a Case Statement.  [Hold on a moment, let me open one of my FPGAs ...].  The Case Statement is driven by an Enum with States "Off", "Setup", and "Run" which appears on the FPGA as a Front Panel Control (called, say, "State") and the "Off" "constant" is wired to the Case Selector, going through a Shift Register.  Here's what the 3 States do:

• Off -- contains the State control, wires it to the right-hand Shift Register.  So "If Off, stay Off unless RIO writes "Setup" or "Run" to State.
• Setup -- contains FPGA Controls that define the desired Waveform (I'm assuming a Pulse Train", including # Pulses and Pulse Timing, including Pulse Width and Pulse Interval.  In particular, the Period (between Pulses), Pulse Width, and # Pulses are wired to Shift Registers (initializing them).  The State local variable is wired to the State shift register (though now that I look at it, I might also want to wire "Off" to the Shift Register ...). 
• Run -- generates the Pulse Train in an "inner" While Loop.  This Loop also has a Case Statement inside it, one that is wired to # Pulses, waiting for it to count down to 0 (which means all the Pulses have been delivered). 
  • 0 case --wire "Off" to the State shift register (to stop the Train) and True to the While Loop to stop the Train.
  • Default -- decrement the Wire holding # Pulses (which basically "counts the Pulses" for you, stopping after N Pulses are delivered.  Deliver one Pulse using a 4-frame Sequence:
    • Frame 1 -- Loop Timer with Period wired to it.
    • Frame 2 -- Set DIO High (assuming a positive Pulse).
    • Frame 3 -- Wait with Pulse Width wired to it.
    • Frame 4 -- Set DIO Low.
• Note that Run, once set into the "State" shift register, gets counted down until the specified # of pulses is delivered.  There is no provision to "abort" the stimulus midway, if this is important, but it is fairly simple and straight-forward FPGA code to write.  In particular, I'm not trying to write SCTL code ...

Bob Schor

[constructionworker]

Thank you for your answer. natasftw

If I understood you correctly, I made an example as follows. This example is for testing purposes only. The logic here is to slow down the timed loop without using timing. Do you mean?

The sensitivity point is important for the frequency. Because it affects the speed. It has to deliver the determined pulses at the determined speed.
For example, if I say send at 150Khz, it literally has to send 150Khz.

[constructionworker]

Thank you for your opinion. Bob_Schor

Let me explain a little bit of the code needed.
-When any number is entered, that number of pulses should be generated and sent at the determined frequency.
-If the number of steps is changed before the number of given steps is over, and if the number of steps is less than the number of steps given before, the stepping is stopped. If the number of changed steps is still greater than the number of steps taken, it reaches the number of new steps and stops, waiting for new steps.

I need to be able to create a frequency between 1-5Mhz and the frequency needs to be changed instantly.

[GerdW]

Hi worker,

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@constructionworker wrote:

The sensitivity point is important for the frequency. Because it affects the speed. It has to deliver the determined pulses at the determined speed.
For example, if I say send at 150Khz, it literally has to send 150Khz.

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How is that image related to your problem? Why is there a TWL using a 1kHz clock? In the beginning you were talking about FPGA code: in the FPGA there are no TWLs!

The usual RIO FPGA has a 40MHz main clock. When generating pulses at 150kHz you need to wait for 267 clock cycles (and will get a 149.8kHz output signal). (You might improve the algorithm by waiting 1×266 cycles and 2×267 cycles, but that also will introduce some jitter to your pulse signal…)

Example:

You "just" need to provide the correct clocks_high/clocks_low values with keeping in mind the wait function will wait for a certain amount of 40MHz main clock cycles!