Hi All,
I am trying to compile and run a piece of logic in th FPGA on a NI7852 Card. I am using Labview 2012 SP1 with Xilinx 13.4 under Windows 7. When I try to do this the xilinx tool complains about running out of memory (takes up 4GB and quits. error Portability:3) This is on a 64bit machine with 16GB ram. It is a small design with an estimated pre-synthesis usage of 10% resources. I am using a custom HDL code in VHDL. Simulating this design with Labview controls attached as well as alone in a seprate testbench works well.
I have installed Xilink 14.7 on the same machine now. However I am not sure how to set up the Labview FPGA server/client to use this tool chain. I have also tried to use the generated encrypted intermidiate files to import the design into ISE 14.7. However, it fails to read modules there and hence cannot start a compilation.
I have attached the encrypted files generated by Labview with this message. I would be grateful if someone could tell me about how to solve this problem.
(With the labview-Xilinkx toolchain i was able to compile and run a counter module(written in VHDL) on FPGA)
Regards
Jude
