Labview 8 Performance , FGV's very very slow. Stuck,Need solution ASAP.

[ashm01]

Steven,

I have done the following exercises and hope the results steer us in a proper direction.

1. I got rid of the 4 extra drivers from the PXI, Rebooted...
2. re-ran the same Example we had issues with. No Change in result.

Then I shifted focus to the examples from the Example finder. I used the Digital port input and output for R series project.

• Since the target was for a PCI R series, I had to create a PXI target and then subsequently an FPGA target.
• Created a host VI and rebinded the FPGA VI and read the Input ports and wrote them also. The result was 5% stable with 7831R.

To Further troubleshoot our problems, I then copied the same VI for the 7833R, recompiled it,created additional references for the second card etc and ran it. The result is attached. This is the first time I am using the 7831&7833R's together, usually they are both the same (either both 7831's or 7833's)

Regards,

AshM01

[Bassett_Hound]

Ashm01,

Thanks for checking the drivers and the example program.  I too was able to get a stable 5% with a 7831R.  Would it be possible for you to post your code you used with the 7831R and 7833R so I can run the same code.  Thanks.

Regards,

Steve

[Duane Mattheisen]

Hello,

  Do you know where I could get some labview code that can  log the CPU usage?

          Thanks Duane

[Duane Mattheisen]

Hi,

  I found the RT Simple CPU Usage.vi but when I tried to run it with Labview 7.1 it could not find "ni_emb.dll".  Do you know where I could get this dll?

               Thanks Duane

[Bassett_Hound]

Hi Duane,

The RT Simple Usage.vi should be used for Real Time targets.  The ni_emb.dll should be located at the following spot: if you have installed RT

 C:\Program Files\National Instruments\LabVIEW 7.1\vi.lib\addons\rt\ETS.

I have attached the library file that contains all the RT Simple Usage VIs.  Have you installed RT with your version of LabVIEW 7.1?

Regards,

S. Bassett

[ashm01]

First of all, let me thank all the people who have tried to help.

Sorry for the LONG absense... Anyway, I have some good news and something unexpected.

Finally after getting sufficient time to try the upgrade procedure again. I came across the following:

• Installed LV 8.0.1 updates and recompiled everything
• As previously mentioned, I am using third party VISA driven communications card in RT. I decided to remove ALL the cards and ALSO the INF's file associated with them.
• After adding the cards individually (one by one) in LV8 the code seems to be better. 

Now the problem:

I used the Number to Boolean array function at numerous places.  what I have noticed is it is slowing the code down to unacceptable levels. This did not hamper much in the previous version. Is there anything different in this version? FYI.. I am trying to convert U8 to a boolean array from my FPGA cards to an array of LED indicators.

• If I break up the code into acquisition and display only it seems to work fine because there is no over head of polling the communications cards.
• If I remove the Boolean Conversion (this includes all communication polling etc) from the code and just display the Numeric values, the updates are quite fast. What gives?

Appreciate your assistance.

Regards,

Ashm01

[Bassett_Hound]

Hi ashmo1,

Good to hear from you again and that your previous FPGA program seems to be running well.  There shouldn't be anything different with the Number to Boolean Array.  Are you implementing the function on your FPGA or on your RT target?  How are you determining the execution time of the function?  How much slower is your program running?

Please let me know the answers to the above questions and I'll be happy to assist you furter.  Take care until then.

Regards,

Steven B.

[ashm01]

Hi Steven,

The setup has changed a bit now, previously I had two PXI RIO boards. Now, just 1 7831R coupled with 2 cRIO 9151 chassis with 8 cRIO modules.

I will try to benchmark the execution time today. I was comparing it to the display update from the RT to the host. After disabling (one by one) all the loops in the RT system, I could pin point to the loop where I converted the values from the FGV's U8 to Boolean array.

• I then tried using the Type casting and manipulate the array using that, it made a little difference but, not satisfactory. 
• Since, this loop is primarily used for display purposes, I slowed it down to 50 ms and it seems OK. (However, would like to improve this)

I have a few queries regarding labview 8:

1. I mass compiled my VI's and got a few errors in the log file, It kinda concerns me... (Attached is the text file)
2. I miss the the Save As (Save with options) to new LLB...  Is this still possible in LV8 or I need to create a build?
3. If the above is possible, I can send you the piece of code.

 Regards,

Ashm01

[ashm01]

Steven,

I did the Benchmarks and the answer is negative! The number to Array conversion does not take up time. However, what is noticed is the front panel updates become very slow and the CPU spikes up. I am assuming that embedded LV is trying to update the UI and it just cant keep up with the updates.

Can't seem to figure what else could be wrong

Regards,

Ashm01

[Bassett_Hound]

Ashm01,

I'll first answer your previous questions from before.  First the compile errors you received when mass compiling is expected behavior.  When mass compiling LabVIEW, the results window may indicate some "Bad VIs". Generally these mass compile messages do not indicate a problem with the LabVIEW 8.0.1 Update installation.  Some VIs that are shipped with LabVIEW will not compile during the Mass compile, for example the FPGA examples will not compile(and you wouldn't want to wait that long either) and will show up as bad VIs.  Second to create .llbs from the project explorer all you need to do is right click the build specification and create a Source Distribution.  This will give you the same functionality as the Save as Source Distribution in 7.1.

Finally, the LabVIEW FPGA Module currently updates the Front Panel as fast as the development computer operating system allows, even if the FPGA VI has not written to indicator.  This is most likely the reason you are seeing a lot of CPU usage.  Ass a side note on FPGA utilization,  every item on the Front Panel of an FPGA VI creates a register so that the host can use it to communicate. This process takes extra gates. If you do not need to communicate with the host make the terminals into constants or global variables will save space on your FPGA device.

I hope this helps out,

Regards,

Steven B.