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LabView, FPGA, FIFO

Hello,

I am trying to construct a program in order to capture temperatures, pressures, etc. I am currently using a cRIO 9073 with c-series modules. The issues arise when trying to vary the data collection rate and writing the data to a CSV file. I cannot seem to figure out how to change the data collection rate using  FIFO mechanism. I know i have to move the FPGA references to the data rate (the counts) into a while loop but in practice it makes it more difficult. I need help distinguishing where the while loop should go and what the operating parameters of the loop should be. As far as writing the data to a CSV file, the data does not transfer into the file at all. The headers come out but the file does not. Any help or direction someone could give would be phenomenal. Thank you for your time and I have attached the FPGA and Main VI files to this question.

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Here is a picture of the data writing. The idea is to record the data after it has been collected, not while it is collecting. 

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Hi Chris,

 


@chris.james117 wrote:

I am currently using a cRIO 9073 with c-series modules. The issues arise when trying to vary the data collection rate and writing the data to a CSV file. … As far as writing the data to a CSV file, the data does not transfer into the file at all.


The cRIO is a computer on its own. It cannot write to the harddrive of your development computer! (You don't want to have other computers access your own drives without any notice, don't you!?)

 

You can save a file in the "harddrive" of your cRIO - or you need to transfer the data from your cRIO to your Windows (?) computer using the network - as is shown in the example projects coming with LabVIEW+RT module!

 


@chris.james117 wrote:

I cannot seem to figure out how to change the data collection rate using  FIFO mechanism.


To change the sample rate you need to set different wait times in your FPGA VI. Right now you are using numeric constants…

 

Btw. both VIs need some cleanup. There is a lot of unneeded or insane code…

And I see no FIFO in the FPGA VI: When you want to read data from this FIFO on the RT side of the project then there must be some other FIFO endpoint in the FPGA!

 

General recommendation: when you want to present code involving RT+FPGA VIs then you should ALWAYS include your LVproj file in the attachment. Best would be to have all code/files in one folder and just attach a ZIP of that folder!

 

Best regards,
GerdW

using LV2011SP1 + LV2017 (+LV2020 sometimes) on Win10+cRIO
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