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LabVIEW FPGA load cell acquisition DMA FIFO

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Hello everyone,

I am trying to acquire data from a load cell, for now in simulation mode. I build an FPGA VI and Real time VI to perform the acquisition, choosing DMA FIFO as intertarget communication for the acquired data. I then tried to plot the data using both waveform graph and chart. One of my problem is that it doesn't seem that the FPGA VI acquires point at the data rate that i set. If i set the loop timer in the FPGA VI code to, for example, 1000000 uSec, i don't seem to get 1 data point each second for each channel, but it looks like i get data point a much higher rate, even if the "tick count" says that the loop is repeating at the rate that i set. In consequence of that i am also having trouble to understand what exacly is the "time" that i display on the graphs and charts. What i would like to see is the amplitude of the points of each channel display in a graph or chart where the real time is flowing in seconds. What am i missing? Does this have to do with the fact that i am in simulation mode and/or is there something wrong mith my code? I attach the FPGA and Real Time VI and their screenshots. Thank you in advance for your attention.

I am using:

-LabVIEW 2019 and the corresponding FPGA and Real Time modules;

-CompactRIO drivers 19.0;

-cRIO9068;

-NI9220 module;

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It seems FPGA timing functions in simulated mode do not reflect the actual target behaviour.
When trying your VI, the loop delay is around 1,6kHz for me whatever input I set in the "Loop Timer" function.

 

A similar thread has already been posted and a piece of NI documentation has been found explaining this behaviour.

 

Since you cannot control the FPGA loop speed, your only possibility is to estimate the time on the host side, but your code will have to be modified specially for simulation mode.

 

Here is an example with your VIs where I estimated the actual FPGA loop frequency.

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Thank you very much for your reply, raphschru. I found the NI documentation about simulated time, maybe I am having some trouble to properly understand that. Anyway, if i understood correctly, there isn't a way to modify the loop rate of the simulated FPGA VI, right? But once I'll compile and run it with the actual FPGA the loop rate that i set will be respected, right? Thank you also for the VI that you attached, it is helping me to understand.

 

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Solution
Accepted by topic author Enomis

@Enomis wrote:

there isn't a way to modify the loop rate of the simulated FPGA VI, right?


None that I know of.
To me the simulated mode only serves to test my FPGA code alone or with a host, but in a "degraded" mode.

 


@Enomis wrote:

But once I'll compile and run it with the actual FPGA the loop rate that i set will be respected, right?


That's right.

I still advise you to measure the actual loop time from within the FPGA and output the value to your host to ensure your loop timing requirement is met.

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Alright. Thank you again, raphschru.

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