LabVIEW FPGA and accessing the PXIe-5764's MGTs

[f_bacon]

Hi,

In the documentation for the PXIe-5764 it mentions that 4 MGTs are available to the user. What's the best way to go about using them? Should this be done through LabVIEW or via Vivado? Is there any documentation available?

Thank you in advance.

[f_bacon]

Does anyone have any information on this topic? I haven't been able to find much regarding this topic on the National Instruments web pages.

Any information would be greatly appreciated.

Thank you.

[NIRebecca]

Hi f_bacon, 

There are LabVIEW examples of MGT communication - have you checked out the MGT Debug Examples.

https://forums.ni.com/t5/Examples-and-IP-for-Software/NI-MGT-Debug-for-the-NI-PXIe-6591R-92R/ta-p/35...

I'd also like to mention there's a Corrective Action Request (CAR #731245) filed for the PXIe-5764 SPECIFICATIONS:

Figure 1. Digital I/O Connector (p4) pin-out A12 and A13 are labelled "MGT REF+ / DIO 0" and "MGT REF- / DIO 1" respectively. These pins should be exclusively "DIO 0" and "DIO 1" and not include anything about MGT REF.

There is an internally generated reference clock fed to the MGT, so there is no need (or support) for an external clock.

Let us know how you get on,

Rebecca

[f_bacon]

Thank you Rebecca, I'll take a look.

I've found the examples: 

NI 793xR - MGT 10 Gbe CLIP

NI 793xR - MGT Aurora CLIP

These seem along the right lines. I suspect I need to create some socketed clip. Using the clip wizard I've ascertained the required signals are:

DioMgtRefClk_p

DioMgtRefClk_n

DioMgtRefClkFromFam

DioMgtRX_n

DioMgtRX_p

DioMgtTX_n

DioMgtTX_p

sDioMgtRefClkFromFamPresent

SocketClk80 

From here I should be able to do what I need to. Please correct me if this isn't the recommended approach. Is there anything written up specifically for this device?

Thanks again.

[f_bacon]

Can you provide any more information regarding the clocks fed to the MGT?

From exporting to Vivado, it seems that the MGTs users have access to are labelled AuxIOMgtRX/TX, with mgt0 at location X1Y19 and ref clk at X1Y4. Using these locations and an input ref clk frequency of 312.5 MHz I am attempting to use an mgt for 10 G Ethernet, but it isn't behaving correctly.

For the Ethernet core to operate, it requires a free running clock for its dclk. Is the LabVIEW user clock free running? To create the socketed clip you have to have the port DioMgtRefClkFromFam, can you tell me what this is?