LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

LabVIEW FPGA: The compilation failed due to exceeding LUTs resources

Solved!
Go to solution
Highlighted

Hi all,
I have a big VHDL code (the code is converted using Matlab tools to HDL). I got "LabVIEW FPGA: The compilation failed due to a Xilinx error" due to exceeding LUTs resources (I am using MyRio 1900).
My question:
Is using component-level IP (CLIP) integration instead of IP integration will reduce the "LUTs resources" usage?

 

I got these comments after importing 50% of my code using IP integration.

 

LabVIEW FPGA: The compilation failed due to a Xilinx error.

Details:
ERROR: [Place 30-640] Place Check : This design requires more Slice LUTs cells than are available in the target device. This design requires 30569 of such cell types but only 17600 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.
ERROR: [Place 30-640] Place Check : This design requires more LUT as Logic cells than are available in the target device. This design requires 29401 of such cell types but only 17600 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.
ERROR: [Place 30-640] Place Check : This design requires more LUT1 and LUT2 and LUT3 and LUT4 and LUT5 and LUT6 and RAMD32 and RAMS32 and SRL16E and SRLC32E cells than are available in the target device. This design requires 36688 of such cell types but only 35200 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ToplevelClkVirt' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [C:/NIFPGA/jobs/X8kue09_Lbc7Dxn/toplevel_gen.xdc:377]
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1571b0fb1

Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1505.305 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 1571b0fb1

Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1505.305 ; gain = 0.000
ERROR: [Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 1571b0fb1

Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1505.305 ; gain = 0.000
14 Infos, 42 Warnings, 0 Critical Warnings and 5 Errors encountered.
place_design failed
report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.561 . Memory (MB): peak = 1505.305 ; gain = 0.000
::ERROR: [Common 17-69] Command failed: Placer could not place all instances

while executing
"place_design -directive "Default""
invoked from within
"if { [catch {place_design -directive "Default"} error_message options] } {
report_utilization -file "toplevel_gen_map.xrpt" -format xml
return..."
(file "C:/NIFPGA/jobs/X8kue09_Lbc7Dxn/place.tcl" line 6)
invoked from within
"source "C:/NIFPGA/jobs/X8kue09_Lbc7Dxn/place.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Thu Sep 10 17:11:21 2020...


Compilation Time
---------------------------
Date submitted: 9/10/2020 5:02 PM
Date results were retrieved: 9/10/2020 5:11 PM
Time waiting in queue: 00:10
Time compiling: 08:52
- Generate Xilinx IP: 00:00
- Synthesize - Vivado: 07:32
- Optimize Logic: 00:43
- Place: 00:25

 

Thanks in advance

0 Kudos
Message 1 of 3
(163 Views)
Solution
Accepted by ashrafayasrah

Is it expected that your code should fit on a myRIO? The "cost-performance" of the myRIO is pretty nice, but it's still an entry-ish level FPGA device.

 

If your code is very large (in FPGA usage) then it just might not be able to fit on this device - the error messages suggest targeting a larger device.

 

If you think the code should be able to fit, or you want to try and fit it in, then you might have some better luck (at least with help on this forum) if you try and convert some of the code to LabVIEW FPGA code directly, rather than importing (V)HDL code.

 

People could then suggest ways that you might be able to reduce the space requirements.

 

I don't know the answer to your direct question (CLIP vs IP), but you can I suppose just try it and see? I don't know that it will help you all that much, but perhaps it's miraculous...


GCentral
0 Kudos
Message 2 of 3
(81 Views)
Highlighted

Thanks for your reply and suggestions
Actually I have tested the code with CLIP and I got the same problem. Unfortunately, I think MyRio 1900 is not suitable for my project so I am planning to use a new microcontroller.

Thank you again

0 Kudos
Message 3 of 3
(65 Views)