LabVIEW FPGA: The compilation failed due to a Xilinx error

[Manu1991]

Please help me to resolve this error

LabVIEW FPGA:  The compilation failed due to a Xilinx error.

Details:

ERROR: [Drc 23-20] Rule violation (PDRC-34) MMCM_adv_ClkFrequency_div_no_dclk - The computed value 2560.000 (CLKIN1_PERIOD, net PllClk40Lcl) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X0Y0 falls outside the operating range of the MMCM VCO frequency for this device (600 - 1200). The computed value is (CLKBFOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input frequency CLKINx_PERIOD (25.000000), multiplication factor CLKFBOUT_MULT_F (64.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

ERROR: [Vivado_Tcl 4-16] Error(s) found during DRC. Router not run.

# exit

INFO: [Common 17-206] Exiting Vivado at Fri Jan 06 11:36:29 2017...

Compilation Time

---------------------------

Date submitted: 06-01-2017 AM 11:07

Date results were retrieved: 06-01-2017 AM 11:36

Time waiting in queue: 00:09

Time compiling: 29:21

- Generate Xilinx IP: 00:00

- Synthesize - Vivado: 14:12

- Optimize Logic: 04:54

- Place: 06:55

- Optimize Timing: 02:45

- Route: 00:13

[Wes_P]

Are you trying to use  a derived clock in your FPGA application? If so, are you sure that the value that you are requesting is possible?

[edjones93]

Hello,

It seems MMCM refers to the Mixed-Mode Clock Manager of a Xilinx chip and is used to derive clocks. As such I have a few questions to get started:

1. What is the hardware you are compiling for?

2. What is the frequencies of any derived clock?

3. Is the Top-Level clock still the base clock or a derived clock?

4. Do you have a timed loop for which you are using a clock and if so, which clock?

5. Could you provide screenshots of your timed loops?

6. If you have any usage of memory of FIFO's in your FPGA code, could you clarify what implementation has been selected for these?

This should provide more context in understanding why your compilation is failing.

Best regards,

Ed

[jiangliang]

I'm having the same problem here.

I'm using SOM 9651, and yes I'm using external clock, the program used to working until I add a derived clock from external clock.

Is it not supported by LabVIEW FPGA or SOM 9651? or maybe there is something I can do to fix this problem.

Thanks, below is the error information.

LabVIEW FPGA: The compilation failed due to a Xilinx error.

Details:
ERROR: [DRC 23-20] Rule violation (PDCN-1568) BUFGCTRL_S_pins_both_connected_to_gnd - For cell window/Bufgce0/GenBufgCtrl.BUFGCTRLx placed at site BUFGCTRL_X0Y20 both S0 and S1 pins are tied to GROUND. Selection of an input clock requires a "select" pair (S0 and CE0, or S1 and CE1) to be asserted High. If either S or CE is not asserted High the desired input will not be selected. Please modify your design.