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LabVIEW FPGA Running Sum w/ Block Memory

Hello,

 

     I am currently developing on the NI7932R FPGA with the NI5753 Adapter Module to capture 8 channels of analog signal. I am capturing 10000 samples for each channel upon rising edge of a trigger signal, and sending that data to block memory (1 memory method for each channel e.g. 10000 samples from channel 1 will be stored in the memory called Ch1_mem, 10000 samples from channel 2 will be stored in the memory called Ch2_mem, etc.):

labview memory.PNG

I also have another set of memory to hold the running sum for each channel:

Labview sum.PNG

After 10 triggers, the running sum is then divided by 10 (averaging the 10000 sample signals captured from 10 triggers). 

 

The issue that I am having, is that the running sum does not actually appear to hold a sum of the captured signals, it appears to only hold the most recently captured signal. I was wondering if anyone has any tips on how to implement a running sum on LabVIEW FPGA. I am new to LabVIEW so I am sure there is a better way to implement this. Or possibly I am misunderstanding how to use the memory methods.

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Do you need the waveform data as well or just the sum?

 

I cannot see the rest of the code but are you using a single cycle timed loop for the BRAM functions?

 

Also BRAM needs a feedback node on the output part; it takes 1-3 cycles depending on the configuration.

 

The code you have could be simulated and run without the AI.  This will save a ton of time on compiles.


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
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Hi Terry_ALE,

 

     Yes, I need the waveform data. So for example, after the 10 triggers, the memory block that contains the running sum for channel 1 should have 10000 elements in it.

 

     I am using a single cycle timed loop to place the sampled data into the memory blocks upon the rising edge of the trigger signal. The part of the code that reads that data out and places it into the running sum memory blocks is in a while loop.

 

     I will try with a feedback node on the BRAM. I may also try changing one of the channels' memory blocks to use LUTs, which I don't believe need feedback nodes.

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Will you need to store more data or is this the maximum you will need to store?

 

Will the data undergo more processing on the FPGA during/after the summing?


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
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I will need to store a variable amount of samples depending on the user input for sample amount from a separate Real Time vi I have. The maximum amount of samples that I want to allow the user to input is 24000. So since the sample amount is variable, I was planning on just using the maximum possible user input to set the memory block size. For now, I had it set to 10000 just to make sure I can get the running sum working first.

 

The only other processing on the FPGA is to divide each sample in the running sum memory blocks by 10 (averaging the waveforms):LabVIEW average.PNG

The averaged waveforms from each channel are then sent to FIFOs so that the Real Time vi can convert the raw ADC codes to voltages, and save that data to SD card.

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Hi Terry_ALE,

 

     I tried your suggestion of simulating my FPGA design, and everything goes as expected in simulation (The sum is calculated properly). However, when I compile the design and do a test with a real signal, the summation does not seem to occur, as I am getting the expected amplitude of waveform / 10. For example, I send a 1Vpp sine to one of the analog channels, and the waveform I am seeing produced by the FPGA design is 0.1Vpp. 

 

     I did not add the feedback nodes since I am only reading from the memory blocks inside of a while loop, and I don't think the read latency affects the memory read inside of a while loop. I did attempt implementing the memory using LUTs but since I have clock domain crossing, the design would not compile.

 

     I am not sure how to properly debug this since the simulation appears to work, but when testing the design with a real signal it does not.

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     I just found out what may be the cause of my problem. I have two modes, one is to capture the signals upon trigger, and the other is to capture signal immediately. When testing in simulation, I was using the immediate capture, but with the real signal I am using trigger mode. So, I just switched the mode to immediate when using the real signal, and the waveform looks as expected. Therefore, the problem must be caused by my implementation of the trigger mode. I will look into this more to see if I can spot any mistakes I made. 

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