LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

LabVIEW FPGA Module 2015 Compilation for PXIe7820 with "no timing"

Solved!
Go to solution

I have made a first compilation for the pxie 7820 with the tool Xilinx Vivado 2014.4 (64bit). The compilation report says "

Compilation completed successfully.

Device Utilization
---------------------------
Total Slices: 19,1% (4848 out of 25350)
Slice Registers: 6,9% (13937 out of 202800)
Slice LUTs: 12,3% (12430 out of 101400)
Block RAMs: 0,9% (3 out of 325)
DSP48s: 6,2% (37 out of 600)

Timing
---------------------------
None.

Compilation Time
---------------------------
Date submitted: 16.07.2016 12:48
Date results were retrieved: 16.07.2016 12:59
Time waiting in queue: 00:08
Time compiling: 10:16
- Generate Xilinx IP: 00:00
- Synthesize - Vivado: 04:18
- Optimize Logic: 00:14
- Place: 01:17
- Optimize Timing: 00:18
- Route: 03:04
- Generate Programming File: 00:56"

What does no timing mean? The onboard clock is 40 MHz. Does it run with this clock? Beacause the compilations for the pci 7833 or pcie 7842 the report shows the maximum clock time.

0 Kudos
Message 1 of 2
(2,819 Views)
Solution
Accepted by topic author Rokot

Hi there,

 

from what I can gather, "none" simply means there are no timing violations. The timing source that will be used is (as you already suspected) the 40 MHz Onboard Clock.

As to why you don't get a mention of the MiteClk and the ReliableClk in the summary, I think it's due to the 7833 and the 7842 relying on Virtex-II and Virtex-5, whereas the 7820 makes use of the Kintex-7 family. Depending which FPGA type you use, different estimates concerning device utilization and timing may not always be available.

Like I said, as long as you don't get a timing error and your compilation finishes successfully, you should be fine.

 

Regards,

 

Alex

Message 2 of 2
(2,734 Views)