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LV FPGA Socketed CLIP workflow w/ NI PXIe-6591R

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It sounds like your workflow is correct in general, but ELF association can be a finicky thing and can vary somewhat across versions of Vivado. What version of Vivado (and LabVIEW FPGA) are you using?

 

If you open the checkpoint you generated in step 10, you should be able to see if the contents of the ELF are still being saved in the BRAM by finding them in the hierarchy and looking at their INIT_## properties. They will be at a location similar to the following:

 

<path from the top of your clip to the microblaze>/mb_system_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram

 

If the INIT_## properties of the BRAMs are all zeroes, then the checkpoint you are handing off to LabVIEW doesn't have your ELF program data associated with it so we will need to figure that out. If the BRAMs are initialized, then we will need to figure out why your Microblaze is non responsive.

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first of all, thank you all for your responses.  I am using labview 2016 and Vivado 2015.4, which matches the version being used by the Xilinx tools for my target - pxie-6592.

 

Am currently reading about data2mem and how it can create a constraints file for me with the contents of the elf file.  I think that makes sense, however I will have to make sure that I use the appropriate clip instance name in my bmm file.

 

 

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data2mem was deprecated and is not available in more recent version of Vivado, I believe starting with 2014.4. You will probably want to stick with the ELF association flow that you are currently using. Once you get it working, it ends up being a much cleaner solution anyway.

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So I have made some progress - and this may be helpful to others - but a Vivado Block Design will not work with the MicroBlaze MCS!  So I tried using Block Design with a MicroBlaze (not MicroBlaze MCS) and I am getting some sort of clock error, but I am not that experienced with using MicroBlaze - yet.  So I will do some reading about the regular MicroBlaze, and when I have a design that works, I will try running it in LabVIEW again and will post my results.  (Possibly in a new thread? I would, but NI makes it super hard to make a new thread, why NI?)... Besides, my Artix-7 fpga development kit arrives tomorrow, so I will try getting a microblaze design working there, and then I will do the same for LabVIEW.

 

For the Xilinx thread, dated November 23rd, 2016, that says that Vivado Block Design does not support Microblaze MCS, go here: https://forums.xilinx.com/t5/Embedded-Development-Tools/SDK-doesn-t-recognize-Microblaze-MCS-in-impo...

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For those still struggling with how to use MicroBlaze and the MicroBlaze MCS with LabVIEW FPGA, I have gotten both to work, and I put most if not all of my code on github, take a look here:

 

https://github.com/JohnStratoudakis/LabVIEW_Fpga

 

I also created a website where I put some full blown tutorials with screen shots.  Once I get out of my current situation where xelab.exe crashes after it passes 4gb of memory, I will be able to update the tutorials and include some videos:

 

http://fpganow.com/

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Well done.

That's exactly the same I'm doing, though with full MicroBlaze (not MCS) I've seen associated ELF files are not actually working... So I usually convert the ELF into XDC constraints with the init values of the BRAMs and pass it to LV within the Socketed CLIP along with the netlists (or DCP).

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