LV FPGA Delay seen between subsequent SCTL's

[nickstorton]

HI All,

I'm developing a custom SPI using LV FPGA and a FlexRIO with a 6581 FAM. The Micro-controller I need to communicate with requires that I write 16 bits of data on a clock rising edge followed by 8 clock cycles to clock the data through the micro and process in the ALU. Then I need to supply a further 16 clocks to clock out the 16 bit result. I have initially done this with 3 Single Cycle Timed Loops, one for each section. I pass the IO references from each SCTL to the next SCTL to get the correct dataflow. When I look at the signals with a logic analyser I can see each of the sections works correctly but there is an approximate 504nS delay between each section of the code. I sort of expected maybe a single clock cycle delay between SCTL's but not this much. Anyone got any ideas on what might be causing this and how I might overcome this issue?

Thanks all,

Nick

[nickstorton]

Hi All,

I’ve been looking a little more into this and have found that if I change the project base clock from the standard 40 MHz clock to the derived 20 MHz clock I am using for the SCTL’s then the delay between the SCTL’s becomes 1 base clock cycle (1/20 MHz = 50 nS). So it would appear that there is an issue when you cross clock boundaries even if you do nothing in between. Anyway with this in mind I can possibly come up with a work around. I will keep you posted.

Thanks,

Nick

[nathand · Accepted solution]

Instead of using several separate SCTLs, consider using one SCTL as a state machine that can handle all three steps.

[nickstorton]

Hi Nathan,

Thanks for the reply. This is the architecture I usually use when writting code running on the PC but for this project on the FPGA, and with it being rather simple, I wanted to write it without the need for "hidden code". I went with this solution to solve the issue in the end, but you always learn something from these issues and that is, that even if the SCTL is using a clock derived from the main base clock, if you cross a clock domain the FPGA compiler will force a re-sync of the clocks and you will get a delay between subsequent code blocks.

Thanks again,

Nick