LABview FPGA 8.6.1 FlexRIO, problem with FPGA banks

[marc8470]

  Hello, I am currently in-company training, I’m working on a flex RIO card (NI-7954), and I have to develop a module (use of the MDK). I try to configure the banks of FPGA. The documentation of kit MDK is rather vague and I do not know if it is possible to use a different reference voltage standard for each banks.

Documentation indicates that the banks 0 and 1 are dependant on the reference voltage standard VccoA, and the banks 2 and 3 of the VccoB voltage. However, the documentation implies that the reference voltage standard can be independent for each banks.

 

I correctly compiled a project besides by modify the file .tbc NI6581Channel module with VccA=1.2V and VccB=1.8V and, the I/O of the bank 0 in LVCMOS12 and the I/O of the banks 1, 2 and 3 in LVCMOS18.

 This last result seems in contradiction with documentation. Is this project valid? (I don't have any module, so can't check the output voltages of the Flex RIO card)  Could you help me? 

Cordially

[BrowningG · Accepted solution]

Hello marc8470,

Each Virtex 5 FPGA bank requires an external voltage reference.  The FlexRIO FPGA module provides this reference in the form of Vccoa and Vccob.  Because there are two voltage references available on the FlexRIO FPGA module, each Vcco reference is connected to 2 IO banks.  The Adapter Module Interface and Protocol chapter of the FlexRIO MDK manual has a table that indicates which GPIO banks are referenced to which Vcco reference.  The Vcco levels set in the general section of the adapter module configuration file are not used by the Xilinx compiler, but instead by the fixed FlexRIO logic to configure the external voltage references.  The IO standard constraints section of the adapter module configuration file is used during compile to configure the output drivers in the Virtex 5.  If the general VccoALevel and VccoBLevel values do not match the IO standard constraints, no error will occur during compile, but the hardware will not be configured correctly during runtime.  The logic families used by each general purpose IO (GPIO) line must match that of the Vcco levels set in the general section of the adapter module configuration file.  A mismatch in values could result to incorrect behavior or possible damage to the FlexRIO FPGA module or the adapter module. 

In the future, please use the email address included in your NI FlexRIO Adapter Module Development Kit (MDK) User Manual to send your questions directly to the FlexRIO MDK support team.  This group has experience with specific FlexRIO MDK questions such as this one. 

The FlexRIO MDK manual is designed to provide all of the information a hardware designer will need to create a FlexRIO adapter module.  National Instruments is always improving and working on new releases of the FlexRIO MDK.  Please feel free to use the support email address in the FlexRIO MDK manual to send me any feedback you have on the contents of the manual.

[marc8470]

Thank you for your help BrowningG

Regards