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Integrating Xilinx IP Cores on LabVIEW FPGA

Hi all,

 

I have been trying to integrate an IP core from the XILINX Core Generator as described in this NI link. The tutorial is actually great because it does exactly what I want to do, implement a FIR filter.

I need to do different things so I need different coefficients for the filter, but for this case I will ignore that and make the example work.

 

So I basically download the example files and proceed to generate the Core with the Xilinx Core Generator. I am running LV 2010 and I get to choose, on the NI FPGA folder between two different versions of the Xilinx ISE (10.1 and 11.5) but for the purpose of my questions this is not relevant as I get the same result in both.

 

The first problem that I encounter is the fact that in the step Generate the IP Core, on the intructions right after Figure 1 I am not able to match the output data dimensions. The tutorial describes the following:

 

"On the second page, select Systolic Multiply Accumulate from the Filter Architecture pull-down menu. The Input Data Width is 16 because the data type is <+/-, 16, 1>. The Output Rounding Mode is Full Precision, and the Output Width is 38. The full precision rounding mode saves all fractional bits of the result. Since the coefficients are quantized as <+/-, 16, 0>, the input data is <+/-, 16, 1>, and the fractional bits count of output is 31. The output data type should be <+/-, 38, 7>. Click the Next button to continue."

 

Well I do that and basically the Output width and fractional bits are automatically calculated (that is good) but they do not match the example (that is not so good). Instead of getting a 38,7 data type I get a 33,1.

 

So I am wondering whether the example is wrong or I did something wrong.

 

So after that what I do is trying to avoid fractional calculations on the FPGA and having all the numbers without fractional bits (all 16,16 or similar). I generate my FIR filter and I am able to successfully compile it to my target (a NI 7952R with a NI 5732 Digitizer). Now the problem I get with this approach is that I do not get functional results. By functional results I mean that the FIR filter I designed (FS 5MHz FC 300 KHz) does not filter properly. In fact it outputs funny signals.

 

I set a multiplexer in my code to either send signals to the DMA FIFO coming directly from the digitizer or having the filter in between the digitizer and the DMA FIFO. On the first case I am able to get signals through properly, meaning the number of samples per cycle matches the combination sampling frequency/input frequency (always pure sines for testing). As soon as I select the FIR filter on my multiplexer the signal goes crazy. Funny enough disabling the input to the FIR filter does not seem to affect the output, so the signals are somehow internally generated.

 

It is relevant to point out that in order to maintain the ranges on the FXP datatypes and to send the data over the DMA FIFO I convert from FXP to FXP or I16 using FXP to boolean array, picking the top 16 bits and converting those either to FXP or to I16.

 

Any help with this issue would be more than welcome!

 

 

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Hello Epsilon,

 

I see that your initial forum post was made almost three weeks ago. I would like to apologize that we didn't respond sooner. Do you still require assistance on this issue?

 

Regards,

Kareem W.
National Instruments
Web Product Manager
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