On a 7975R FlexRIO FPGA card I'm sending a fixed buffer of data through a FIFO to a Python Node under LabVIEW running on Red Hat 8. All of the data is going into the buffer, and then I fire an interrupt which the Python waits for. However, I don't know the size of the data array until I read it in Python and pass it to LabVIEW. What I'm finding is that sometimes not all of the data is read. I tried the trick of reading zero elements and then having the read tell me how many elements are remaining, which presumably is all of the data. But the read returns elements remaining even though no new data has been pushed into the FIFO. Is there a design pattern or something about the FPGA Python interface where I can determine that all of the data has streamed across the DMA and read the entire buffer at once? I'm looking at around >130,000 I16 elements, but it could vary, and like I mentioned I don't know the size until I read it.
Code snippet in Python (FPGA was opened elsewhere):
ReadFIFO():
global session
target_to_host = session.fifos['The FIFO']
read_value=target_to_host.read(0, timeout_ms=100)
amount_to_get = read_value.elements_remaining
read_value2 = target_to_host.read(amount_to_get, timeout_ms=10)
return ((read_value2.data, read_value2.elements_remaining))
read_value2.elements_remaining will sometimes be non-zero.
