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In FPGA compile i get error "ERROR:ConstraintSystem:58"

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I am using the Xilinx LogiCore IP generator to generate DSP IP for my FPGA.

The problem is that the names for the generated components are to long.

On the NI website http://digital.ni.com/public.nsf/allkb/F810E4289A420FE68625796600764C66

It describes an issue very similar to what I am having ID issue 309260 "Compile error (ERROR:ConstraintSystem:58) when compiling a LabVIEW FPGA VI that contains a VI generated from a DSP diagram."

 

I followed the suggestions and changed all of my IP to names such as "A" and "B". At first this did not work, only moving the entire project to a different shorter directory path did this work.

 

Now when I regenerate the IP from "Tools">>"FPGA Modules">>"Regenerate IP Node" This will rename my IP with an additional random name at the end. So, if I look in my folder not only will I have "A.vhd" but now I will also have "A_F27AB4F7464E508DCCB219B2C4271B18.vhd"

This is very repeatable and you should be able to reproduce this.

 

This is causing havoc with our software control tool and with our software release process. Our software data base can only accommodate file names of a certain length, and this is violating this. Also, I now have to files with the exact same content but with different names.

 

Do you have a patch for this issue as indicated on your website?

 

Regards,

 

 

 

 


Engineering - The art of applied creativity  ~Theo Sutton
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Hello MrQuestion,

 

When you're regenerating your IP Integration Node support files, are you regenerating them from files that in the same directory as existing IP support files? Or are you moving your files and then regenerating the IP in a new directory with now .vhd files in it?

Colden
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I am not moving them.

This seems to be an issue with all DSP based IP logiCore generated code.

 

So lets say i have  LogiCore generated code called "A".

If you look in the directory that the code is placed in you will see "A.XCO"

inside this file you will see a parameter called

"CSET component_name=A"

 

Now regenerate your IP Logic from the top level VI by opening your top level VI click on Tools>>FPGA Module>>Regenerate IP Intigration Node Support Files

 

After the regeneration you will see that the previous line in the "A.XCO" has changed to something like the following

"CSET component_name=A_F27AB4F7464E508DCCB219B2C4271B18"

 

And you now have several extra files in that same directory including a new file called "A_F27AB4F7464E508DCCB219B2C4271B18.XCO"

 

These long file names are causing issues with our software revision tools and software release process.


Engineering - The art of applied creativity  ~Theo Sutton
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You should delete the old generated files before regenerating IP integration node support files. This renaming is happening so that it doesn't overwrite old versions of the support files.

Colden
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I'm not so sure about it renaming to prevent overwriting old files. I say this because if I change the IP later, and it needs to regenerate the IP the tool seems perfectly happy overwriting the old files as long as they have the long random name in it. 

 

When I look at how the Xilinx ISE uses the LogiCore tool there are several command line parameters that you can send to it from your development enviroment. In this case it appears that LabVIEW is sending a comand line parameter that insist on having this random name and some how LabVIEW remembers this random name even if you change it within the LogiCore enviroment.

 

There must be someway to change how LabVIEW communicates to the Xilinx LogiCore tool.

 

 


Engineering - The art of applied creativity  ~Theo Sutton
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So, Really?

Am I the only one that get this error?  "ERROR:ConstraintSystem:58 - Constraint"

I get several errors that go along the lines,

 

 

'ERROR:ConstraintSystem:58 - Constraint <INST
   "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x2B00MHz/*HandshakeSLV_Ackx/*iLcl
   StoredData*" TNM =
   TNM_iLclStoredData_TimeLoopCoreFromRioClk40ToRioClk40Derived5x2B00MHz/*Handsh
   akeSLV_Ackx;> [Puma15Top.ucf(666)]: INST
   "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x2B00MHz/*HandshakeSLV_Ackx/*iLcl
   StoredData*" does not match any design objects.'

 

This really has no meaning to me, and no direction to the LabVIEW code.

I have no that this error is comming until i'm an hour and a half into the compile.

😞


Engineering - The art of applied creativity  ~Theo Sutton
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Hello MrQuestion,

 

It looks like you've opened up a service request with us. I'll work with the engineer handling that service request, and we'll try and handle this issue there.

Colden
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I am getting this exact same error now. Did you ever get a resolution to this issues Colden/MrQuestion?

 

 

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Solution
Accepted by topic author MrQuestion

I ended up using LogiCore externally. If you do a search in your LabVIEW FPGA tools folder you should find  "\Xilinx12_4\ISE\bin\nt\coregen.exe" (in the folder of the specific version of Xilinx tools that you have installed) This is the Xilinx Logicore exe without the National Instruments candy wrapper.

 

I created all of my LogicCore external to LabVIEW (this actually made life easer, the LogicCore tool has a better manager to track all of your LogicCore IP anyways)  and then used the IP nodes within LabVIEW to access the IP.

This prevented the long names, and now i can better manage the IP because I can place the code into any folder that I want to without breaking LabVIEW.

 

--good luck


Engineering - The art of applied creativity  ~Theo Sutton
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I have the same issue in LabVIEW FPGA 2013.  I'm trying to compile a small vi for a FAm module that we are developping.

 

ERROR:ConstraintSystem:58 - Constraint <INST
   "*DmaPortCommIfcLvFpgaIrq*bIpIrq_ms*" TNM = TNM_Custom79;>
   [PumaK7Top.ucf(760)]: INST "*DmaPortCommIfcLvFpgaIrq*bIpIrq_ms*" does not
   match any design objects.

 

What's was the solution?  

 

Regards.

 

Patrick

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