Implementing Xillinx Vivado's 7 Series FPGAs Transceivers as a LabVIEW FPGA's CLIP (PXIe-6591).

[jmarques]

With LabVIEW FPGA[0], I see that the example "NI 6591 FIFO example" uses Aurora 64b66b IP[1] as a CLIP to receive and send the I/O data in chunks of 64 bits.

However, this implementation does not meet my needs since I need at least to pattern match start/end-of-lines (K28.1/5) and decode 8b10b at line rate.

Xillinx Vivado's provides the 7 Series FPGAs Transceivers Wizard IP[2] to configure the high-speed serial transceiver in Kinter-7,
which match many of my requirements with the possibility to adapt the VHDL to my needs.

I read the "NI High-Speed Serial Instruments User Manual"[3], specially Chapter 8, where insights on how to create a custom CLIP are provided.
Despite this, without further information, I can not figure out how to proceed implementing the 7 Series FPGAs Transceivers Wizard IP into a CLIP.

Could someone with more experience in wrapping VHDL code into custom CLIPs give me some help?
Or straight up estimate the viability of using NI hardware for this application?

Any examples that handle the I/O (Port 0 and 1) at a "lower level"/"bit per bit stream" would also be useful.
Or how the Aurora 64b66b IP from example "NI 6591 FIFO example" was wrapped as a CLIP (Vivado -> LabVIEW, not importing the provided VHDL code).

[0] Software: LabVIEW SP1 FPGA 2020 and Vivado 2019.1
[1] https://docs.xilinx.com/v/u/en-US/aurora_64b66b_ds528
[2] https://docs.xilinx.com/v/u/en-US/pg168-gtwizard
[3] https://www.ni.com/docs/en-US/bundle/pxie-6591-6592-7902-features/resource/374574f.pdf

Looking forward to any response,

[jmarques]

The ESIstream example [1] helped me implement what I needed.

I used Vivado 2019.1 and the 7 Series FPGAs Transceivers Wizard [2] [3] to generate the IPs with the configurations that I needed (simplex, independent channels in the same quad).

Then I generated the example design for one of the IPs and modified it to include the others IPs, which you can simulate to check if everything is ok.

Tip: When modifying IPs use the TCL command "set_property IS_MANAGED false [get_files <THE_IP>.xci" instead of modifying outside Vivado, this will forbid Vivado from rewriting your files while allowing you to edit the IPs' source files.

After that, I had to create a wrapper for the IPs for each side of the channel, then instance in another wrapper (the CLIP) ([1] explains this part).

At LabVIEW, I modified the ESIstream, stripping off all features I didn't need and implementing what I needed; at this step I preferred to write RTL in VHDL and use IP integrator to import to LabVIEW, since it gave me more freedom to run test benches on them.

End note:

I had to use Vivado way more than LabVIEW's documentation seems to suggest, but that is not a problem!

[1] https://forums.ni.com/t5/Examples-and-IP-for-Software/ESIstream-example-for-the-NI-PXIe-6591R-92R-an...

[2] https://docs.xilinx.com/api/khub/maps/U2GQR49CyPTcdLAya2_2Xg/attachments/EgORb~RntbG58TmXl2ifhQ/cont...

[3] https://docs.xilinx.com/api/khub/documents/SgVweevU5cLv0LyXoCVoPg/content?Ft-Calling-App=ft%2Ftu...