My interest is in doing dsp in the fpga's of the reconfigurable USRP software defined radios. I hate to risk an age-old flame fest but I'm coming out of the closet: I use local variables in lieu of long wires. I know it's frowned on but when you've got reset, enable, trigger, and clock signals going to lots of blocks it can rapidly become a rats nest. And bundling things up in clusters and sub vi's only hides the mess. It's still there. And it makes re-use much harder. I've browsed the 'proper' code in the examples and it looks nice but it's awfully hard to follow the signal you most care about and it's a nightmare to change. In SDR there's usually only one data path and I don't use LV's for data, just for ancillary signals like resets, enables, etc. I always use them the same way: write to an indicator in one place (usually a block that creates all these signals) and read local variables linked to the indicator in many places. I never write to local variables. So what do I risk ? Is the compiler smart enough to see through this and wire them up during optimization?

Using LVs in SCTLs add a cycle of latency to the datapath. It's basically pipelining. LVs written in Cycle X will only have that value read in Cycle X+1. If all of your other datapaths are synchronised, this can be a big problem.

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LabVIEW

If LVFPGA, can i avoid race conditions in a SCTL by only reading local variables

Solved!

@Intaris wrote:

AEs won't work in a SCTL will they?

I never thought of that. I forgot we're talking about single cycles and timing.

Bill

(Mid-Level minion.)
My support system ensures that I don't look totally incompetent.
Proud to say that I've progressed beyond knowing just enough to be dangerous. I now know enough to know that I have no clue about anything at all.
Humble author of the CLAD Nugget.

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LabVIEW

If LVFPGA, can i avoid race conditions in a SCTL by only reading local variables

Re: If LVFPGA, can i avoid race conditions in a SCTL by only reading local variables