Hi sfzheng,
so you write to some controls on the RT side of your project.
And the FPGA reads from those controls and writes their values into the AO node.
Why do you expect "in phase" writing controls on RT side to reading controls on FPGA side?
You might think about using a FIFO to send data from RT to FPGA and have the FPGA handle the data on its own!?
Best regards,
GerdW
using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019