I was wondering if I am on the right track with a solution to a vexing problem. I am trying to implement 160MHz clocked point to point serial bus with clock and DDR data on a PXIe7971R FlexRIO using an NI 6583 adapter module.
The tricky part is that we must shift the clock edges by 90 degrees versus the data edges. If this was lower speed I would just run the FlexRIO at 4x the clock rate, but it’s tough to close timing at 4 x 160 MHz. We also will likely need to make small adjustments to that skew, to make up for delay differences in the paths elsewhere in the design.
I was going to make a copy of the socketed CLIP and instantiate a Xilinx ODELAYE2 and IDELAYCTRL library component between the IO coming out of the VI pin assignments and the module pins. Does this sound like a reasonable approach? Are there any other suggestions on how to approach this?
I would assume that as clock rates rise and we approach the setup and hold times of external components that our FlexRIOs are talking to, that there are others facing the same issues