Hello,
I am a beginner of labview FPGA. Now I am trying to build a PLL on FPGA module PXI-7831R.
At first, I found a an example vi from http://decibel.ni.com/content/docs/DOC-1762, Lock in Amplifier on LabVIEW FPGA, which has a PLL subvi. It is baseon cRIO-9233, I made some changes to run it on pxi-7831R and it works now. But there are some problems that I don't understand as following:
1. Why do it have 'nominal frequency' and 'alpha' paramaters? They don't exist in a real lock-in-amplifier instrument.
2. With sample method, there will be some problem in cross zero part especially for the 'detect frequency' vi. It starts the counter when the sampled reuslts go from minus to plus. But sometimes, just after one or two points, there maybe be a minus value again. So, the counter will be just 2 or 3,thus the frequency is much large than it should be. I think the reasons are from the sample rate and sample accuary.
Could anybody please help me to realize a PLL without the above problem? JK-flipflop maybe a better solution for phase dector. But I am not clear how to realize the whole system. you suggestion will be appreciated.
Thank you.
Akun.
