Hi to all,
I am new in this forum. We implemented a TDC designed in VHDL. On the Xilinx Kintex7 Evaluation Board works nicely. We dream to interface it directly into "VI" LabView.
The complicate thing is that the design VHDL is able to measure time with a precision magnitude of order higher of the clock used. In other words the input can not be sampled with a clock!
To simplify, my VHDL entity have the follow interface:
- clock as INPUT
- reset as INPUT
- data_out as OUTPUT (clocked)
- data_valid as OUTPUT (clocked)
- input_channel (must be NOT CLOCKED)
Should I use CLIP (Component-Level IP) or IP Block?
Does it exists a way in LabView to connect a FPGA input pin to VHDL "input_channel" directly without be sampled by a clock?
In both case how I suppose to connect the FPGA input to the "VHDL" input: inside a timed-loop sounds to me that the digital input is sampled with the loop clock, inside a normal loop no idea when actually is called and outside a loop the "call" is done just once...
Any idea or suggestions?
Thank you in advance,
We developed a VHDL design and it runs smoothly on the Kintex7 FPGAs. I would like to direct interface it in LabView.
Some inputs of it must completely asynchronous, so they must be not sampled by a clock.
I tried this outside, inside a loop but it does not work:
Does it exists a way to route an FPGA input directly asynchronously to a VHDL code by using CLIP or IP-Block on the PXIe-7822R or PXIe-7856R?