How to clear Host to Target FIFO

[bsayiner]

Hi guys. In cRIO RT I'm getting data from ethernet and i pass this data to fpga for logic output via Host To Target FIFO. But if i run application second time previous data still in the fifo and junk output generated from digital output. How can i clear host side and fpga side fifo.

Thanks

[Vincent90]

Hi,

Use FPGA reset invoke node.

BR,

Vincent

[speleato]

Reset is simple and works, but has other side effects, which may or may not be desireable. 

As another option and to avoid these side effects, you can also simply read the FIFO until it is empty either when shutting down the first time or when starting up the second time.

Sebastian